mirror of https://gitee.com/openkylin/linux.git
drm/i915: ValleyView IRQ support
ValleyView has a new interrupt architecture; best to put it in a new set of functions. Also make sure the ring mask functions handle ValleyView. FIXME: fix flipping; need to enable interrupts and call prepare/finish Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes
Daniel Vetter
parent
c46ce4d7e6
commit
7e231dbe0c
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@ -468,7 +468,45 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
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if (ret)
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return ret;
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if (!HAS_PCH_SPLIT(dev)) {
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if (IS_VALLEYVIEW(dev)) {
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seq_printf(m, "Display IER:\t%08x\n",
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I915_READ(VLV_IER));
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seq_printf(m, "Display IIR:\t%08x\n",
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I915_READ(VLV_IIR));
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seq_printf(m, "Display IIR_RW:\t%08x\n",
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I915_READ(VLV_IIR_RW));
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seq_printf(m, "Display IMR:\t%08x\n",
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I915_READ(VLV_IMR));
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for_each_pipe(pipe)
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seq_printf(m, "Pipe %c stat:\t%08x\n",
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pipe_name(pipe),
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I915_READ(PIPESTAT(pipe)));
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seq_printf(m, "Master IER:\t%08x\n",
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I915_READ(VLV_MASTER_IER));
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seq_printf(m, "Render IER:\t%08x\n",
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I915_READ(GTIER));
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seq_printf(m, "Render IIR:\t%08x\n",
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I915_READ(GTIIR));
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seq_printf(m, "Render IMR:\t%08x\n",
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I915_READ(GTIMR));
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seq_printf(m, "PM IER:\t\t%08x\n",
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I915_READ(GEN6_PMIER));
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seq_printf(m, "PM IIR:\t\t%08x\n",
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I915_READ(GEN6_PMIIR));
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seq_printf(m, "PM IMR:\t\t%08x\n",
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I915_READ(GEN6_PMIMR));
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seq_printf(m, "Port hotplug:\t%08x\n",
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I915_READ(PORT_HOTPLUG_EN));
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seq_printf(m, "DPFLIPSTAT:\t%08x\n",
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I915_READ(VLV_DPFLIPSTAT));
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seq_printf(m, "DPINVGTT:\t%08x\n",
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I915_READ(DPINVGTT));
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} else if (!HAS_PCH_SPLIT(dev)) {
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seq_printf(m, "Interrupt enable: %08x\n",
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I915_READ(IER));
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seq_printf(m, "Interrupt identity: %08x\n",
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@ -120,6 +120,10 @@ void intel_enable_asle(struct drm_device *dev)
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long irqflags;
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/* FIXME: opregion/asle for VLV */
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if (IS_VALLEYVIEW(dev))
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return;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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if (HAS_PCH_SPLIT(dev))
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@ -426,6 +430,119 @@ static void gen6_pm_rps_work(struct work_struct *work)
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mutex_unlock(&dev_priv->dev->struct_mutex);
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}
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static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 iir, gt_iir, pm_iir;
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irqreturn_t ret = IRQ_NONE;
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unsigned long irqflags;
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int pipe;
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u32 pipe_stats[I915_MAX_PIPES];
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u32 vblank_status;
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int vblank = 0;
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bool blc_event;
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atomic_inc(&dev_priv->irq_received);
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vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
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PIPE_VBLANK_INTERRUPT_STATUS;
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while (true) {
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iir = I915_READ(VLV_IIR);
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gt_iir = I915_READ(GTIIR);
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pm_iir = I915_READ(GEN6_PMIIR);
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if (gt_iir == 0 && pm_iir == 0 && iir == 0)
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goto out;
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ret = IRQ_HANDLED;
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if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
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notify_ring(dev, &dev_priv->ring[RCS]);
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if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[VCS]);
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if (gt_iir & GT_BLT_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[BCS]);
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if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
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GT_GEN6_BSD_CS_ERROR_INTERRUPT |
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GT_RENDER_CS_ERROR_INTERRUPT)) {
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DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
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i915_handle_error(dev, false);
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}
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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for_each_pipe(pipe) {
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int reg = PIPESTAT(pipe);
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pipe_stats[pipe] = I915_READ(reg);
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/*
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* Clear the PIPE*STAT regs before the IIR
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*/
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if (pipe_stats[pipe] & 0x8000ffff) {
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if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
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DRM_DEBUG_DRIVER("pipe %c underrun\n",
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pipe_name(pipe));
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I915_WRITE(reg, pipe_stats[pipe]);
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}
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}
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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/* Consume port. Then clear IIR or we'll miss events */
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if (iir & I915_DISPLAY_PORT_INTERRUPT) {
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u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
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DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
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hotplug_status);
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if (hotplug_status & dev_priv->hotplug_supported_mask)
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queue_work(dev_priv->wq,
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&dev_priv->hotplug_work);
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I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
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I915_READ(PORT_HOTPLUG_STAT);
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}
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if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
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drm_handle_vblank(dev, 0);
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vblank++;
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if (!dev_priv->flip_pending_is_done) {
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intel_finish_page_flip(dev, 0);
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}
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}
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if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
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drm_handle_vblank(dev, 1);
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vblank++;
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if (!dev_priv->flip_pending_is_done) {
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intel_finish_page_flip(dev, 0);
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}
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}
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if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
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blc_event = true;
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if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->rps_lock, flags);
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WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
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dev_priv->pm_iir |= pm_iir;
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I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
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POSTING_READ(GEN6_PMIMR);
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spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
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queue_work(dev_priv->wq, &dev_priv->rps_work);
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}
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I915_WRITE(GTIIR, gt_iir);
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I915_WRITE(GEN6_PMIIR, pm_iir);
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I915_WRITE(VLV_IIR, iir);
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}
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out:
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return ret;
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}
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static void pch_irq_handler(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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@ -1567,6 +1684,32 @@ static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
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return 0;
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}
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static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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u32 dpfl, imr;
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if (!i915_pipe_enabled(dev, pipe))
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return -EINVAL;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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dpfl = I915_READ(VLV_DPFLIPSTAT);
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imr = I915_READ(VLV_IMR);
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if (pipe == 0) {
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dpfl |= PIPEA_VBLANK_INT_EN;
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imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
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} else {
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dpfl |= PIPEA_VBLANK_INT_EN;
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imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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}
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I915_WRITE(VLV_DPFLIPSTAT, dpfl);
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I915_WRITE(VLV_IMR, imr);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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return 0;
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}
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/* Called from drm generic code, passed 'crtc' which
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* we use as a pipe index
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*/
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@ -1608,6 +1751,28 @@ static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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u32 dpfl, imr;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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dpfl = I915_READ(VLV_DPFLIPSTAT);
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imr = I915_READ(VLV_IMR);
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if (pipe == 0) {
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dpfl &= ~PIPEA_VBLANK_INT_EN;
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imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
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} else {
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dpfl &= ~PIPEB_VBLANK_INT_EN;
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imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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}
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I915_WRITE(VLV_IMR, imr);
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I915_WRITE(VLV_DPFLIPSTAT, dpfl);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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/* Set the vblank monitor pipe
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*/
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int i915_vblank_pipe_set(struct drm_device *dev, void *data,
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@ -1817,6 +1982,53 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
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POSTING_READ(SDEIER);
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}
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static void valleyview_irq_preinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int pipe;
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atomic_set(&dev_priv->irq_received, 0);
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INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
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INIT_WORK(&dev_priv->error_work, i915_error_work_func);
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/* VLV magic */
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I915_WRITE(VLV_IMR, 0);
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I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
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I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
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I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
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if (IS_GEN6(dev) || IS_GEN7(dev)) {
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/* Workaround stalls observed on Sandy Bridge GPUs by
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* making the blitter command streamer generate a
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* write to the Hardware Status Page for
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* MI_USER_INTERRUPT. This appears to serialize the
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* previous seqno write out before the interrupt
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* happens.
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*/
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I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
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I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
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}
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/* and GT */
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, 0xffffffff);
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I915_WRITE(GTIER, 0x0);
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POSTING_READ(GTIER);
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I915_WRITE(DPINVGTT, 0xff);
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I915_WRITE(PORT_HOTPLUG_EN, 0);
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I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
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for_each_pipe(pipe)
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I915_WRITE(PIPESTAT(pipe), 0xffff);
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I915_WRITE(VLV_IIR, 0xffffffff);
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I915_WRITE(VLV_IMR, 0xffffffff);
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I915_WRITE(VLV_IER, 0x0);
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POSTING_READ(VLV_IER);
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}
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/*
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* Enable digital hotplug on the PCH, and configure the DP short pulse
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* duration to 2ms (which is the minimum in the Display Port spec)
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@ -1963,6 +2175,96 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
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return 0;
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}
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static int valleyview_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 render_irqs;
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u32 enable_mask;
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u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
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u16 msid;
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enable_mask = I915_DISPLAY_PORT_INTERRUPT;
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enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
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I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
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dev_priv->irq_mask = ~enable_mask;
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DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
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DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
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DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
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dev_priv->pipestat[0] = 0;
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dev_priv->pipestat[1] = 0;
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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/* Hack for broken MSIs on VLV */
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pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
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pci_read_config_word(dev->pdev, 0x98, &msid);
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msid &= 0xff; /* mask out delivery bits */
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msid |= (1<<14);
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pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
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I915_WRITE(VLV_IMR, dev_priv->irq_mask);
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I915_WRITE(VLV_IER, enable_mask);
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I915_WRITE(VLV_IIR, 0xffffffff);
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I915_WRITE(PIPESTAT(0), 0xffff);
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I915_WRITE(PIPESTAT(1), 0xffff);
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POSTING_READ(VLV_IER);
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I915_WRITE(VLV_IIR, 0xffffffff);
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I915_WRITE(VLV_IIR, 0xffffffff);
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render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
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GT_GEN6_BLT_CS_ERROR_INTERRUPT |
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GT_BLT_USER_INTERRUPT |
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GT_GEN6_BSD_USER_INTERRUPT |
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GT_GEN6_BSD_CS_ERROR_INTERRUPT |
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GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
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GT_PIPE_NOTIFY |
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GT_RENDER_CS_ERROR_INTERRUPT |
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GT_SYNC_STATUS |
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GT_USER_INTERRUPT;
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dev_priv->gt_irq_mask = ~render_irqs;
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, 0);
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I915_WRITE(GTIER, render_irqs);
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POSTING_READ(GTIER);
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/* ack & enable invalid PTE error interrupts */
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#if 0 /* FIXME: add support to irq handler for checking these bits */
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I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
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I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
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#endif
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I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
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#if 0 /* FIXME: check register definitions; some have moved */
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/* Note HDMI and DP share bits */
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if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMIB_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMIC_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
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hotplug_en |= HDMID_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
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hotplug_en |= SDVOC_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
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hotplug_en |= SDVOB_HOTPLUG_INT_EN;
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if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
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hotplug_en |= CRT_HOTPLUG_INT_EN;
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hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
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}
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#endif
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I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
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return 0;
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}
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static void i915_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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@ -2066,6 +2368,30 @@ static int i915_driver_irq_postinstall(struct drm_device *dev)
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return 0;
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}
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static void valleyview_irq_uninstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int pipe;
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if (!dev_priv)
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return;
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||||
dev_priv->vblank_pipe = 0;
|
||||
|
||||
for_each_pipe(pipe)
|
||||
I915_WRITE(PIPESTAT(pipe), 0xffff);
|
||||
|
||||
I915_WRITE(HWSTAM, 0xffffffff);
|
||||
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
||||
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
||||
for_each_pipe(pipe)
|
||||
I915_WRITE(PIPESTAT(pipe), 0xffff);
|
||||
I915_WRITE(VLV_IIR, 0xffffffff);
|
||||
I915_WRITE(VLV_IMR, 0xffffffff);
|
||||
I915_WRITE(VLV_IER, 0x0);
|
||||
POSTING_READ(VLV_IER);
|
||||
}
|
||||
|
||||
static void ironlake_irq_uninstall(struct drm_device *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
|
|
@ -2121,7 +2447,8 @@ void intel_irq_init(struct drm_device *dev)
|
|||
{
|
||||
dev->driver->get_vblank_counter = i915_get_vblank_counter;
|
||||
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
||||
if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
|
||||
if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
|
||||
IS_VALLEYVIEW(dev)) {
|
||||
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
|
||||
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
|
||||
}
|
||||
|
|
@ -2132,7 +2459,14 @@ void intel_irq_init(struct drm_device *dev)
|
|||
dev->driver->get_vblank_timestamp = NULL;
|
||||
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
|
||||
|
||||
if (IS_IVYBRIDGE(dev)) {
|
||||
if (IS_VALLEYVIEW(dev)) {
|
||||
dev->driver->irq_handler = valleyview_irq_handler;
|
||||
dev->driver->irq_preinstall = valleyview_irq_preinstall;
|
||||
dev->driver->irq_postinstall = valleyview_irq_postinstall;
|
||||
dev->driver->irq_uninstall = valleyview_irq_uninstall;
|
||||
dev->driver->enable_vblank = valleyview_enable_vblank;
|
||||
dev->driver->disable_vblank = valleyview_disable_vblank;
|
||||
} else if (IS_IVYBRIDGE(dev)) {
|
||||
/* Share pre & uninstall handlers with ILK/SNB */
|
||||
dev->driver->irq_handler = ivybridge_irq_handler;
|
||||
dev->driver->irq_preinstall = ironlake_irq_preinstall;
|
||||
|
|
|
|||
|
|
@ -510,6 +510,11 @@
|
|||
#define IIR 0x020a4
|
||||
#define IMR 0x020a8
|
||||
#define ISR 0x020ac
|
||||
#define VLV_IIR_RW 0x182084
|
||||
#define VLV_IER 0x1820a0
|
||||
#define VLV_IIR 0x1820a4
|
||||
#define VLV_IMR 0x1820a8
|
||||
#define VLV_ISR 0x1820ac
|
||||
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
|
||||
#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
|
||||
#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
|
||||
|
|
@ -2533,7 +2538,7 @@
|
|||
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
|
||||
#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
|
||||
|
||||
#define DPFLIPSTAT_VLV 0x70028
|
||||
#define VLV_DPFLIPSTAT 0x70028
|
||||
#define PIPEB_LINE_COMPARE_STATUS (1<<29)
|
||||
#define PIPEB_HLINE_INT_EN (1<<28)
|
||||
#define PIPEB_VBLANK_INT_EN (1<<27)
|
||||
|
|
|
|||
|
|
@ -687,7 +687,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
|
|||
|
||||
spin_lock(&ring->irq_lock);
|
||||
if (ring->irq_refcount++ == 0) {
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
|
||||
ironlake_enable_irq(dev_priv,
|
||||
GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
|
||||
else
|
||||
|
|
@ -706,7 +706,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
|
|||
|
||||
spin_lock(&ring->irq_lock);
|
||||
if (--ring->irq_refcount == 0) {
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
|
||||
ironlake_disable_irq(dev_priv,
|
||||
GT_USER_INTERRUPT |
|
||||
GT_PIPE_NOTIFY);
|
||||
|
|
|
|||
Loading…
Reference in New Issue