mirror of https://gitee.com/openkylin/linux.git
drm etnaviv and exynos for rc1
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJcJBeKAAoJEAx081l5xIa+6hYQAIpVqfcYBStXae/Ta4DhXTZ0 oAq685LhHOXrG2tsas50gw05w30g9GZUgcRcrbDiITdeiyoZfB0DNQY6bdc64+o8 X9EwGr4ZOK/Gm+Q6Z97FRTNARbKopm2RyNvZ4znn++Me7xrs32rx/SaL6ZAK9PpQ bqHeq1yMhJtOpj2eJZaUt2dcnY1fuQBx3saCR6B3sEDNEQpUwEISeThJvXsAhRB/ h9jO0yf9fb5wjO9alOIA3Nv7nB6h5XR+A6pyF396h8lUYZSTNBZL/Q6tPP1F6qSh l+SPLUI2U41ufkdGJfxmyWyt3b39TWslntCIUQF4FmZA3a7G+LsW8vihQqiZl8cv y6+Aoq5tA4uN9+mq0hRWS2bSXOLlxfRO8g58NRl+NhJG5T/i54vFAS/MfeR8zI+g dsjIYWRT4pu130qKP4Vj8iGpvSfvyqmZF5innlbJB3ruWOQf3pGFiuB6IghOindk trneV5homRCQgSwBHFx+YuOBNrYXeHUIyylyMB3IQXN02W7uLFmZUbwxBgiE1Aje cpy5OhOz39tDpDqSuJ0Lu7wjroqGEQ7DxIdCd2iq3ZpbStavqpiAtksaLa8dKVsl JrpJSZtF/0dYM7QZyGp3YHriL2FPR5TTiCzpdc+R8JDk3kraqV+pWAkpXxG6UK6a cjktD1xat7od4rGzQAcb =N74f -----END PGP SIGNATURE----- Merge tag 'drm-next-2018-12-27' of git://anongit.freedesktop.org/drm/drm Pull more drm updates from Dave Airlie: "Daniel collected a couple of pulls after I want on holidays, back for a couple of days, so may as well send them out. This has exynos and etnaviv work for 4.21. exynos: - plane alpha and blending configurability etnaviv: - mostly cleanups in prep for new features" * tag 'drm-next-2018-12-27' of git://anongit.freedesktop.org/drm/drm: drm/etnaviv: remove lastctx member from gpu struct drm/etnaviv: replace header include with forward declaration drm/etnaviv: remove unnecessary local irq disable drm/exynos: fimd: Make pixel blend mode configurable drm/exynos: fimd: Make plane alpha configurable drm/etnaviv: Replace drm_dev_unref with drm_dev_put drm/etnaviv: consolidate hardware fence handling in etnaviv_gpu drm/etnaviv: kill active fence tracking
This commit is contained in:
Linus Torvalds
commit
7e59fad9c9
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@ -439,6 +439,4 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
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if (drm_debug & DRM_UT_DRIVER)
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etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
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gpu->lastctx = cmdbuf->ctx;
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}
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@ -72,14 +72,8 @@ static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file)
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for (i = 0; i < ETNA_MAX_PIPES; i++) {
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struct etnaviv_gpu *gpu = priv->gpu[i];
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if (gpu) {
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mutex_lock(&gpu->lock);
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if (gpu->lastctx == ctx)
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gpu->lastctx = NULL;
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mutex_unlock(&gpu->lock);
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if (gpu)
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drm_sched_entity_destroy(&ctx->sched_entity[i]);
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}
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}
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kfree(ctx);
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@ -523,7 +517,7 @@ static int etnaviv_bind(struct device *dev)
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if (!priv) {
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dev_err(dev, "failed to allocate private data\n");
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ret = -ENOMEM;
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goto out_unref;
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goto out_put;
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}
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drm->dev_private = priv;
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@ -549,7 +543,7 @@ static int etnaviv_bind(struct device *dev)
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component_unbind_all(dev, drm);
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out_bind:
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kfree(priv);
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out_unref:
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out_put:
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drm_dev_put(drm);
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return ret;
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@ -107,17 +107,6 @@ static inline size_t size_vstruct(size_t nelem, size_t elem_size, size_t base)
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return base + nelem * elem_size;
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}
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/* returns true if fence a comes after fence b */
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static inline bool fence_after(u32 a, u32 b)
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{
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return (s32)(a - b) > 0;
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}
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static inline bool fence_after_eq(u32 a, u32 b)
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{
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return (s32)(a - b) >= 0;
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}
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/*
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* Etnaviv timeouts are specified wrt CLOCK_MONOTONIC, not jiffies.
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* We need to calculate the timeout in terms of number of jiffies
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@ -3,10 +3,12 @@
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* Copyright (C) 2015-2018 Etnaviv Project
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/dma-fence.h>
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#include <linux/moduleparam.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/thermal.h>
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#include "etnaviv_cmdbuf.h"
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@ -976,7 +978,6 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
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void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
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{
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unsigned long flags;
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unsigned int i = 0;
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dev_err(gpu->dev, "recover hung GPU!\n");
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@ -989,15 +990,13 @@ void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
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etnaviv_hw_reset(gpu);
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/* complete all events, the GPU won't do it after the reset */
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spin_lock_irqsave(&gpu->event_spinlock, flags);
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spin_lock(&gpu->event_spinlock);
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for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
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complete(&gpu->event_free);
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bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
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spin_unlock_irqrestore(&gpu->event_spinlock, flags);
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gpu->completed_fence = gpu->active_fence;
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spin_unlock(&gpu->event_spinlock);
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etnaviv_gpu_hw_init(gpu);
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gpu->lastctx = NULL;
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gpu->exec_state = -1;
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mutex_unlock(&gpu->lock);
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@ -1032,7 +1031,7 @@ static bool etnaviv_fence_signaled(struct dma_fence *fence)
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{
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struct etnaviv_fence *f = to_etnaviv_fence(fence);
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return fence_completed(f->gpu, f->base.seqno);
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return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
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}
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static void etnaviv_fence_release(struct dma_fence *fence)
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@ -1071,6 +1070,12 @@ static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
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return &f->base;
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}
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/* returns true if fence a comes after fence b */
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static inline bool fence_after(u32 a, u32 b)
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{
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return (s32)(a - b) > 0;
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}
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/*
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* event management:
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*/
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@ -1078,7 +1083,7 @@ static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
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static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
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unsigned int *events)
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{
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unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
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unsigned long timeout = msecs_to_jiffies(10 * 10000);
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unsigned i, acquired = 0;
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for (i = 0; i < nr_events; i++) {
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@ -1095,7 +1100,7 @@ static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
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timeout = ret;
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}
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spin_lock_irqsave(&gpu->event_spinlock, flags);
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spin_lock(&gpu->event_spinlock);
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for (i = 0; i < nr_events; i++) {
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int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
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@ -1105,7 +1110,7 @@ static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
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set_bit(event, gpu->event_bitmap);
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}
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spin_unlock_irqrestore(&gpu->event_spinlock, flags);
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spin_unlock(&gpu->event_spinlock);
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return 0;
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@ -1118,18 +1123,11 @@ static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
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static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpu->event_spinlock, flags);
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if (!test_bit(event, gpu->event_bitmap)) {
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dev_warn(gpu->dev, "event %u is already marked as free",
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event);
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spin_unlock_irqrestore(&gpu->event_spinlock, flags);
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} else {
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clear_bit(event, gpu->event_bitmap);
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spin_unlock_irqrestore(&gpu->event_spinlock, flags);
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complete(&gpu->event_free);
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}
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}
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@ -1306,8 +1304,6 @@ struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
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goto out_unlock;
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}
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gpu->active_fence = gpu_fence->seqno;
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if (submit->nr_pmrs) {
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gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
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kref_get(&submit->refcount);
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@ -1549,7 +1545,6 @@ static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
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etnaviv_gpu_update_clock(gpu);
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etnaviv_gpu_hw_init(gpu);
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gpu->lastctx = NULL;
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gpu->exec_state = -1;
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mutex_unlock(&gpu->lock);
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@ -1806,8 +1801,8 @@ static int etnaviv_gpu_rpm_suspend(struct device *dev)
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struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
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u32 idle, mask;
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/* If we have outstanding fences, we're not idle */
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if (gpu->completed_fence != gpu->active_fence)
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/* If there are any jobs in the HW queue, we're not idle */
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if (atomic_read(&gpu->sched.hw_rq_count))
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return -EBUSY;
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/* Check whether the hardware (except FE) is idle */
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@ -6,9 +6,6 @@
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#ifndef __ETNAVIV_GPU_H__
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#define __ETNAVIV_GPU_H__
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_drv.h"
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@ -88,6 +85,8 @@ struct etnaviv_event {
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struct etnaviv_cmdbuf_suballoc;
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struct etnaviv_cmdbuf;
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struct regulator;
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struct clk;
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#define ETNA_NR_EVENTS 30
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@ -98,7 +97,6 @@ struct etnaviv_gpu {
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struct mutex lock;
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struct etnaviv_chip_identity identity;
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enum etnaviv_sec_mode sec_mode;
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struct etnaviv_file_private *lastctx;
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struct workqueue_struct *wq;
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struct drm_gpu_scheduler sched;
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@ -121,7 +119,6 @@ struct etnaviv_gpu {
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struct mutex fence_lock;
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struct idr fence_idr;
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u32 next_fence;
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u32 active_fence;
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u32 completed_fence;
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wait_queue_head_t fence_event;
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u64 fence_context;
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@ -161,11 +158,6 @@ static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
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return readl(gpu->mmio + reg);
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}
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static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
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{
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return fence_after_eq(gpu->completed_fence, fence);
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}
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int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
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int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
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@ -228,6 +228,21 @@ static const uint32_t fimd_formats[] = {
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DRM_FORMAT_ARGB8888,
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};
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static const unsigned int capabilities[WINDOWS_NR] = {
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0,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
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};
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static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
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u32 val)
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{
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val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
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writel(val, ctx->regs + reg);
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}
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static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
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{
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struct fimd_context *ctx = crtc->ctx;
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@ -551,13 +566,88 @@ static void fimd_commit(struct exynos_drm_crtc *crtc)
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writel(val, ctx->regs + VIDCON0);
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}
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static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
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unsigned int alpha, unsigned int pixel_alpha)
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{
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u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
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u32 val = 0;
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switch (pixel_alpha) {
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case DRM_MODE_BLEND_PIXEL_NONE:
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case DRM_MODE_BLEND_COVERAGE:
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val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
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val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
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break;
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case DRM_MODE_BLEND_PREMULTI:
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default:
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if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
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val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
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val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
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} else {
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val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
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val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
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}
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break;
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}
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fimd_set_bits(ctx, BLENDEQx(win), mask, val);
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}
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static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
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unsigned int alpha, unsigned int pixel_alpha)
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{
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u32 win_alpha_l = (alpha >> 8) & 0xf;
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u32 win_alpha_h = alpha >> 12;
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u32 val = 0;
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switch (pixel_alpha) {
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case DRM_MODE_BLEND_PIXEL_NONE:
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break;
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case DRM_MODE_BLEND_COVERAGE:
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case DRM_MODE_BLEND_PREMULTI:
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default:
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val |= WINCON1_ALPHA_SEL;
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val |= WINCON1_BLD_PIX;
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val |= WINCON1_ALPHA_MUL;
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break;
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}
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fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
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/* OSD alpha */
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val = VIDISD14C_ALPHA0_R(win_alpha_h) |
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VIDISD14C_ALPHA0_G(win_alpha_h) |
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VIDISD14C_ALPHA0_B(win_alpha_h) |
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VIDISD14C_ALPHA1_R(0x0) |
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VIDISD14C_ALPHA1_G(0x0) |
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VIDISD14C_ALPHA1_B(0x0);
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writel(val, ctx->regs + VIDOSD_C(win));
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val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
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VIDW_ALPHA_B(win_alpha_l);
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writel(val, ctx->regs + VIDWnALPHA0(win));
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val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
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VIDW_ALPHA_B(0x0);
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writel(val, ctx->regs + VIDWnALPHA1(win));
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|
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fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
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BLENDCON_NEW_8BIT_ALPHA_VALUE);
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}
|
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|
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static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
|
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uint32_t pixel_format, int width)
|
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struct drm_framebuffer *fb, int width)
|
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{
|
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unsigned long val;
|
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struct exynos_drm_plane plane = ctx->planes[win];
|
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struct exynos_drm_plane_state *state =
|
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to_exynos_plane_state(plane.base.state);
|
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uint32_t pixel_format = fb->format->format;
|
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unsigned int alpha = state->base.alpha;
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u32 val = WINCONx_ENWIN;
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unsigned int pixel_alpha;
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val = WINCONx_ENWIN;
|
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if (fb->format->has_alpha)
|
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pixel_alpha = state->base.pixel_blend_mode;
|
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else
|
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pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
|
||||
|
||||
/*
|
||||
* In case of s3c64xx, window 0 doesn't support alpha channel.
|
||||
|
|
@ -591,8 +681,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
|
|||
break;
|
||||
case DRM_FORMAT_ARGB8888:
|
||||
default:
|
||||
val |= WINCON1_BPPMODE_25BPP_A1888
|
||||
| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
|
||||
val |= WINCON1_BPPMODE_25BPP_A1888;
|
||||
val |= WINCONx_WSWP;
|
||||
val |= WINCONx_BURSTLEN_16WORD;
|
||||
break;
|
||||
|
|
@ -610,25 +699,12 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
|
|||
val &= ~WINCONx_BURSTLEN_MASK;
|
||||
val |= WINCONx_BURSTLEN_4WORD;
|
||||
}
|
||||
|
||||
writel(val, ctx->regs + WINCON(win));
|
||||
fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
|
||||
|
||||
/* hardware window 0 doesn't support alpha channel. */
|
||||
if (win != 0) {
|
||||
/* OSD alpha */
|
||||
val = VIDISD14C_ALPHA0_R(0xf) |
|
||||
VIDISD14C_ALPHA0_G(0xf) |
|
||||
VIDISD14C_ALPHA0_B(0xf) |
|
||||
VIDISD14C_ALPHA1_R(0xf) |
|
||||
VIDISD14C_ALPHA1_G(0xf) |
|
||||
VIDISD14C_ALPHA1_B(0xf);
|
||||
|
||||
writel(val, ctx->regs + VIDOSD_C(win));
|
||||
|
||||
val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
|
||||
VIDW_ALPHA_G(0xf);
|
||||
writel(val, ctx->regs + VIDWnALPHA0(win));
|
||||
writel(val, ctx->regs + VIDWnALPHA1(win));
|
||||
fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
|
||||
fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -785,7 +861,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc,
|
|||
DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
|
||||
}
|
||||
|
||||
fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
|
||||
fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
|
||||
|
||||
/* hardware window 0 doesn't support color key. */
|
||||
if (win != 0)
|
||||
|
|
@ -987,6 +1063,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
|
|||
ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
|
||||
ctx->configs[i].zpos = i;
|
||||
ctx->configs[i].type = fimd_win_types[i];
|
||||
ctx->configs[i].capabilities = capabilities[i];
|
||||
ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
|
||||
&ctx->configs[i]);
|
||||
if (ret)
|
||||
|
|
|
|||
|
|
@ -198,6 +198,7 @@
|
|||
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
|
||||
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
|
||||
#define WINCONx_ENWIN (1 << 0)
|
||||
#define WINCONx_BLEND_MODE_MASK (0xc2)
|
||||
|
||||
#define WINCON0_BPPMODE_MASK (0xf << 2)
|
||||
#define WINCON0_BPPMODE_SHIFT 2
|
||||
|
|
@ -211,6 +212,7 @@
|
|||
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
|
||||
|
||||
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
|
||||
#define WINCON1_ALPHA_MUL (1 << 7)
|
||||
#define WINCON1_BLD_PIX (1 << 6)
|
||||
#define WINCON1_BPPMODE_MASK (0xf << 2)
|
||||
#define WINCON1_BPPMODE_SHIFT 2
|
||||
|
|
@ -437,6 +439,14 @@
|
|||
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
|
||||
|
||||
/* Blending equation control */
|
||||
#define BLENDEQx(_win) (0x244 + ((_win - 1) * 4))
|
||||
#define BLENDEQ_ZERO 0x0
|
||||
#define BLENDEQ_ONE 0x1
|
||||
#define BLENDEQ_ALPHA_A 0x2
|
||||
#define BLENDEQ_ONE_MINUS_ALPHA_A 0x3
|
||||
#define BLENDEQ_ALPHA0 0x6
|
||||
#define BLENDEQ_B_FUNC_F(_x) (_x << 6)
|
||||
#define BLENDEQ_A_FUNC_F(_x) (_x << 0)
|
||||
#define BLENDCON 0x260
|
||||
#define BLENDCON_NEW_MASK (1 << 0)
|
||||
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue