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gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware 

It's a bit hard to realize what the BAR1 is for and what is the layout
of the data in it. Be slightly more verbose to better show how GPIO and
IRQ bases are derived from the hardware.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Andy Shevchenko 2020-04-08 18:41:55 +03:00
parent 6b1c7837af
commit 7e73aa90a3
1 changed files with 2 additions and 2 deletions
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4
drivers/gpio/gpio-merrifield.c
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@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
base = pcim_iomap_table(pdev)[1]; base = pcim_iomap_table(pdev)[1];
irq_base = readl(base); irq_base = readl(base + 0 * sizeof(u32));
gpio_base = readl(sizeof(u32) + base); gpio_base = readl(base + 1 * sizeof(u32));
/* Release the IO mapping, since we already get the info from BAR1 */ /* Release the IO mapping, since we already get the info from BAR1 */
pcim_iounmap_regions(pdev, BIT(1)); pcim_iounmap_regions(pdev, BIT(1));