mirror of https://gitee.com/openkylin/linux.git
iio: imu: st_lsm6dsx: move irq related definitions in irq_config
Group irq related definition in irq_config structure in st_lsm6dsx_settings. This is a preliminary patch to move OpenDrain/Active low registers in st_lsm6dsx_settings. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Tested-by: Sean Nyekjaer <sean@geanix.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Lorenzo Bianconi
Jonathan Cameron
parent
a912ee4c91
commit
7e9061030d
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@ -238,29 +238,21 @@ struct st_lsm6dsx_ext_dev_settings {
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/**
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* struct st_lsm6dsx_settings - ST IMU sensor settings
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* @wai: Sensor WhoAmI default value.
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* @int1_addr: Control Register address for INT1
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* @int2_addr: Control Register address for INT2
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* @reset_addr: register address for reset/reboot
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* @max_fifo_size: Sensor max fifo length in FIFO words.
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* @id: List of hw id/device name supported by the driver configuration.
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* @channels: IIO channels supported by the device.
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* @irq_config: interrupts related registers.
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* @odr_table: Hw sensors odr table (Hz + val).
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* @fs_table: Hw sensors gain table (gain + val).
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* @decimator: List of decimator register info (addr + mask).
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* @batch: List of FIFO batching register info (addr + mask).
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* @lir: Latched interrupt register info (addr + mask).
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* @clear_on_read: Clear on read register info (addr + mask).
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* @fifo_ops: Sensor hw FIFO parameters.
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* @ts_settings: Hw timer related settings.
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* @shub_settings: i2c controller related settings.
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*/
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struct st_lsm6dsx_settings {
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u8 wai;
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u8 int1_addr;
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u8 int2_addr;
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u8 int1_func_addr;
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u8 int2_func_addr;
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u8 int_func_mask;
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u8 reset_addr;
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u16 max_fifo_size;
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struct {
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@ -271,12 +263,18 @@ struct st_lsm6dsx_settings {
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const struct iio_chan_spec *chan;
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int len;
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} channels[2];
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struct {
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struct st_lsm6dsx_reg irq1;
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struct st_lsm6dsx_reg irq2;
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struct st_lsm6dsx_reg irq1_func;
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struct st_lsm6dsx_reg irq2_func;
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struct st_lsm6dsx_reg lir;
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struct st_lsm6dsx_reg clear_on_read;
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} irq_config;
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struct st_lsm6dsx_odr_table_entry odr_table[2];
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struct st_lsm6dsx_fs_table_entry fs_table[2];
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struct st_lsm6dsx_reg decimator[ST_LSM6DSX_MAX_ID];
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struct st_lsm6dsx_reg batch[ST_LSM6DSX_MAX_ID];
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struct st_lsm6dsx_reg lir;
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struct st_lsm6dsx_reg clear_on_read;
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struct st_lsm6dsx_fifo_ops fifo_ops;
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struct st_lsm6dsx_hw_ts_settings ts_settings;
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struct st_lsm6dsx_shub_settings shub_settings;
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@ -361,9 +359,9 @@ struct st_lsm6dsx_hw {
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u8 ts_sip;
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u8 sip;
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const struct st_lsm6dsx_reg *irq_routing;
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u8 event_threshold;
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u8 enable_event;
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struct st_lsm6dsx_reg irq_routing;
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u8 *buff;
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@ -61,7 +61,6 @@
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#include "st_lsm6dsx.h"
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#define ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK BIT(3)
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#define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
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#define ST_LSM6DSX_REG_RESET_MASK BIT(0)
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#define ST_LSM6DSX_REG_BOOT_MASK BIT(7)
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@ -97,8 +96,6 @@ static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = {
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static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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{
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.wai = 0x68,
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.int1_addr = 0x0c,
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.int2_addr = 0x0d,
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.reset_addr = 0x22,
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.max_fifo_size = 32,
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.id = {
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@ -166,14 +163,19 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 3,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0c,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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},
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},
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{
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.wai = 0x69,
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.int1_addr = 0x0d,
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.int2_addr = 0x0e,
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.int1_func_addr = 0x5e,
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.int2_func_addr = 0x5f,
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.int_func_mask = BIT(5),
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.reset_addr = 0x12,
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.max_fifo_size = 1365,
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.id = {
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@ -242,6 +244,28 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 4,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0e,
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.mask = BIT(3),
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},
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.lir = {
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.addr = 0x58,
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.mask = BIT(0),
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},
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.irq1_func = {
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.addr = 0x5e,
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.mask = BIT(5),
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},
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.irq2_func = {
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.addr = 0x5f,
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.mask = BIT(5),
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},
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},
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.decimator = {
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[ST_LSM6DSX_ID_ACC] = {
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.addr = 0x08,
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@ -252,10 +276,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.mask = GENMASK(5, 3),
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},
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},
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.lir = {
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.addr = 0x58,
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.mask = BIT(0),
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},
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.fifo_ops = {
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.update_fifo = st_lsm6dsx_update_fifo,
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.read_fifo = st_lsm6dsx_read_fifo,
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@ -301,11 +321,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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},
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{
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.wai = 0x69,
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.int1_addr = 0x0d,
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.int2_addr = 0x0e,
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.int1_func_addr = 0x5e,
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.int2_func_addr = 0x5f,
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.int_func_mask = BIT(5),
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.reset_addr = 0x12,
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.max_fifo_size = 682,
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.id = {
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@ -374,6 +389,28 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 4,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0e,
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.mask = BIT(3),
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},
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.lir = {
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.addr = 0x58,
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.mask = BIT(0),
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},
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.irq1_func = {
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.addr = 0x5e,
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.mask = BIT(5),
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},
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.irq2_func = {
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.addr = 0x5f,
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.mask = BIT(5),
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},
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},
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.decimator = {
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[ST_LSM6DSX_ID_ACC] = {
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.addr = 0x08,
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@ -384,10 +421,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.mask = GENMASK(5, 3),
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},
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},
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.lir = {
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.addr = 0x58,
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.mask = BIT(0),
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},
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.fifo_ops = {
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.update_fifo = st_lsm6dsx_update_fifo,
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.read_fifo = st_lsm6dsx_read_fifo,
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@ -433,11 +466,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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},
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{
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.wai = 0x6a,
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.int1_addr = 0x0d,
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.int2_addr = 0x0e,
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.int1_func_addr = 0x5e,
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.int2_func_addr = 0x5f,
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.int_func_mask = BIT(5),
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.reset_addr = 0x12,
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.max_fifo_size = 682,
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.id = {
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@ -515,6 +543,28 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 4,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0e,
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.mask = BIT(3),
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},
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.lir = {
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.addr = 0x58,
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.mask = BIT(0),
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},
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.irq1_func = {
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.addr = 0x5e,
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.mask = BIT(5),
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},
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.irq2_func = {
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.addr = 0x5f,
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.mask = BIT(5),
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},
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},
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.decimator = {
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[ST_LSM6DSX_ID_ACC] = {
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.addr = 0x08,
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@ -525,10 +575,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.mask = GENMASK(5, 3),
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},
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},
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.lir = {
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.addr = 0x58,
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.mask = BIT(0),
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},
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.fifo_ops = {
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.update_fifo = st_lsm6dsx_update_fifo,
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.read_fifo = st_lsm6dsx_read_fifo,
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@ -578,8 +624,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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},
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{
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.wai = 0x6c,
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.int1_addr = 0x0d,
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.int2_addr = 0x0e,
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.reset_addr = 0x12,
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.max_fifo_size = 512,
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.id = {
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@ -651,6 +695,24 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 4,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0e,
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.mask = BIT(3),
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},
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.lir = {
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.addr = 0x56,
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.mask = BIT(0),
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},
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.clear_on_read = {
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.addr = 0x56,
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.mask = BIT(6),
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},
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},
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.batch = {
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[ST_LSM6DSX_ID_ACC] = {
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.addr = 0x09,
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@ -661,14 +723,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.mask = GENMASK(7, 4),
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},
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},
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.lir = {
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.addr = 0x56,
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.mask = BIT(0),
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},
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.clear_on_read = {
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.addr = 0x56,
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.mask = BIT(6),
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},
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.fifo_ops = {
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.update_fifo = st_lsm6dsx_update_fifo,
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.read_fifo = st_lsm6dsx_read_tagged_fifo,
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@ -721,11 +775,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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},
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{
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.wai = 0x6b,
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.int1_addr = 0x0d,
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.int2_addr = 0x0e,
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.int1_func_addr = 0x5e,
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.int2_func_addr = 0x5f,
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.int_func_mask = BIT(5),
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.reset_addr = 0x12,
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.max_fifo_size = 512,
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.id = {
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@ -794,6 +843,32 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 4,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0e,
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.mask = BIT(3),
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},
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.lir = {
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.addr = 0x56,
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.mask = BIT(0),
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},
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.clear_on_read = {
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.addr = 0x56,
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.mask = BIT(6),
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},
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.irq1_func = {
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.addr = 0x5e,
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.mask = BIT(5),
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},
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.irq2_func = {
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.addr = 0x5f,
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.mask = BIT(5),
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},
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},
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.batch = {
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[ST_LSM6DSX_ID_ACC] = {
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.addr = 0x09,
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@ -804,14 +879,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.mask = GENMASK(7, 4),
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},
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},
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.lir = {
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.addr = 0x56,
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.mask = BIT(0),
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},
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.clear_on_read = {
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.addr = 0x56,
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.mask = BIT(6),
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},
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.fifo_ops = {
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.update_fifo = st_lsm6dsx_update_fifo,
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.read_fifo = st_lsm6dsx_read_tagged_fifo,
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@ -853,11 +920,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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},
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{
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.wai = 0x6b,
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.int1_addr = 0x0d,
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.int2_addr = 0x0e,
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.int1_func_addr = 0x5e,
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.int2_func_addr = 0x5f,
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.int_func_mask = BIT(5),
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.reset_addr = 0x12,
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.max_fifo_size = 512,
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.id = {
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@ -929,6 +991,32 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.fs_len = 4,
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},
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},
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.irq_config = {
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.irq1 = {
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.addr = 0x0d,
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.mask = BIT(3),
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},
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.irq2 = {
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.addr = 0x0e,
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.mask = BIT(3),
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},
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.lir = {
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.addr = 0x56,
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.mask = BIT(0),
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},
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.clear_on_read = {
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.addr = 0x56,
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.mask = BIT(6),
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},
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.irq1_func = {
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.addr = 0x5e,
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.mask = BIT(5),
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},
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.irq2_func = {
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.addr = 0x5f,
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.mask = BIT(5),
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},
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},
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.batch = {
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[ST_LSM6DSX_ID_ACC] = {
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.addr = 0x09,
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@ -939,14 +1027,6 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
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.mask = GENMASK(7, 4),
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},
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},
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.lir = {
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.addr = 0x56,
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.mask = BIT(0),
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},
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.clear_on_read = {
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.addr = 0x56,
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.mask = BIT(6),
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},
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.fifo_ops = {
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.update_fifo = st_lsm6dsx_update_fifo,
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.read_fifo = st_lsm6dsx_read_tagged_fifo,
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@ -1296,7 +1376,7 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state)
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int err;
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u8 enable = 0;
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if (!hw->settings->int1_func_addr)
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if (!hw->settings->irq_config.irq1_func.addr)
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return -ENOTSUPP;
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enable = state ? hw->settings->event_settings.enable_reg.mask : 0;
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@ -1308,12 +1388,11 @@ static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state)
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if (err < 0)
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return err;
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enable = state ? hw->irq_routing.mask : 0;
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enable = state ? hw->irq_routing->mask : 0;
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/* Enable wakeup interrupt */
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return regmap_update_bits(hw->regmap, hw->irq_routing.addr,
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hw->irq_routing.mask,
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enable);
|
||||
return regmap_update_bits(hw->regmap, hw->irq_routing->addr,
|
||||
hw->irq_routing->mask, enable);
|
||||
}
|
||||
|
||||
static int st_lsm6dsx_read_event(struct iio_dev *iio_dev,
|
||||
|
|
@ -1537,7 +1616,9 @@ static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
|
|||
return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin);
|
||||
}
|
||||
|
||||
static int st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, u8 *drdy_reg)
|
||||
static int
|
||||
st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw,
|
||||
const struct st_lsm6dsx_reg **drdy_reg)
|
||||
{
|
||||
int err = 0, drdy_pin;
|
||||
|
||||
|
|
@ -1551,14 +1632,12 @@ static int st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw, u8 *drdy_reg)
|
|||
|
||||
switch (drdy_pin) {
|
||||
case 1:
|
||||
*drdy_reg = hw->settings->int1_addr;
|
||||
hw->irq_routing.addr = hw->settings->int1_func_addr;
|
||||
hw->irq_routing.mask = hw->settings->int_func_mask;
|
||||
hw->irq_routing = &hw->settings->irq_config.irq1_func;
|
||||
*drdy_reg = &hw->settings->irq_config.irq1;
|
||||
break;
|
||||
case 2:
|
||||
*drdy_reg = hw->settings->int2_addr;
|
||||
hw->irq_routing.addr = hw->settings->int2_func_addr;
|
||||
hw->irq_routing.mask = hw->settings->int_func_mask;
|
||||
hw->irq_routing = &hw->settings->irq_config.irq2_func;
|
||||
*drdy_reg = &hw->settings->irq_config.irq2;
|
||||
break;
|
||||
default:
|
||||
dev_err(hw->dev, "unsupported data ready pin\n");
|
||||
|
|
@ -1654,7 +1733,7 @@ static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)
|
|||
|
||||
static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
|
||||
{
|
||||
u8 drdy_int_reg;
|
||||
const struct st_lsm6dsx_reg *reg;
|
||||
int err;
|
||||
|
||||
/* device sw reset */
|
||||
|
|
@ -1683,35 +1762,29 @@ static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
|
|||
return err;
|
||||
|
||||
/* enable FIFO watermak interrupt */
|
||||
err = st_lsm6dsx_get_drdy_reg(hw, &drdy_int_reg);
|
||||
err = st_lsm6dsx_get_drdy_reg(hw, ®);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
err = regmap_update_bits(hw->regmap, drdy_int_reg,
|
||||
ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK,
|
||||
FIELD_PREP(ST_LSM6DSX_REG_FIFO_FTH_IRQ_MASK,
|
||||
1));
|
||||
err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
|
||||
ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* enable Latched interrupts for device events */
|
||||
if (hw->settings->lir.addr) {
|
||||
unsigned int data;
|
||||
|
||||
data = ST_LSM6DSX_SHIFT_VAL(1, hw->settings->lir.mask);
|
||||
err = regmap_update_bits(hw->regmap, hw->settings->lir.addr,
|
||||
hw->settings->lir.mask, data);
|
||||
if (hw->settings->irq_config.lir.addr) {
|
||||
reg = &hw->settings->irq_config.lir;
|
||||
err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
|
||||
ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/* enable clear on read for latched interrupts */
|
||||
if (hw->settings->clear_on_read.addr) {
|
||||
data = ST_LSM6DSX_SHIFT_VAL(1,
|
||||
hw->settings->clear_on_read.mask);
|
||||
if (hw->settings->irq_config.clear_on_read.addr) {
|
||||
reg = &hw->settings->irq_config.clear_on_read;
|
||||
err = regmap_update_bits(hw->regmap,
|
||||
hw->settings->clear_on_read.addr,
|
||||
hw->settings->clear_on_read.mask,
|
||||
data);
|
||||
reg->addr, reg->mask,
|
||||
ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue