mirror of https://gitee.com/openkylin/linux.git
[media] drx-j: Use checkpatch --fix to solve several issues
Instead of manually fixing the issues, use the --fix experimental checkpatch. That solves a bunch of checkpatch issues. Acked-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
dbe82e0613
commit
7ef66759a3
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@ -70,10 +70,10 @@ DEFINES
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#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
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#define TUNER_MODE_SUB_MAX 8
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#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
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#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
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TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
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TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
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TUNER_MODE_SUB6 | TUNER_MODE_SUB7 )
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TUNER_MODE_SUB6 | TUNER_MODE_SUB7)
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/*------------------------------------------------------------------------------
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TYPEDEFS
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@ -37,4 +37,4 @@ struct drx39xxj_state {
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extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c);
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#endif // DVB_DUMMY_FE_H
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#endif /* DVB_DUMMY_FE_H */
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@ -114,9 +114,9 @@ int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr,
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struct i2c_msg msg[2] = {
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{.addr = wDevAddr->i2cAddr,
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.flags = 0,.buf = wData,.len = wCount},
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.flags = 0, .buf = wData, .len = wCount},
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{.addr = rDevAddr->i2cAddr,
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.flags = I2C_M_RD,.buf = rData,.len = rCount},
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.flags = I2C_M_RD, .buf = rData, .len = rCount},
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};
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printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
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@ -252,29 +252,29 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
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addr &= ~DRXDAP_FASI_FLAGS;
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addr |= flags;
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#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
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( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
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#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \
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(DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) )
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/* short format address preferred but long format otherwise */
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if (DRXDAP_FASI_LONG_FORMAT(addr)) {
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#endif
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#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
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#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
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buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
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buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
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buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
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buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
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#endif
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#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
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( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
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#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \
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(DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) )
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} else {
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#endif
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#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
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#if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
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buf[bufx++] = (u8) ((addr << 1) & 0xFF);
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buf[bufx++] =
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(u8) (((addr >> 16) & 0x0F) |
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((addr >> 18) & 0xF0));
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#endif
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#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
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( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
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#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \
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(DRXDAPFASI_SHORT_ADDR_ALLOWED == 1) )
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}
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#endif
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@ -332,7 +332,7 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
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{
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int rc = DRX_STS_ERROR;
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#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
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#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
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if (rdata == NULL) {
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return DRX_STS_INVALID_ARG;
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}
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@ -478,29 +478,29 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
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/* Buffer device address */
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addr &= ~DRXDAP_FASI_FLAGS;
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addr |= flags;
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#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
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( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
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#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \
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((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) )
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/* short format address preferred but long format otherwise */
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if (DRXDAP_FASI_LONG_FORMAT(addr)) {
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#endif
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#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 )
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#if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
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buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
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buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
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buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
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buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
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#endif
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#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
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( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
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#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \
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((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) )
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} else {
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#endif
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#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 )
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#if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
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buf[bufx++] = (u8) ((addr << 1) & 0xFF);
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buf[bufx++] =
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(u8) (((addr >> 16) & 0x0F) |
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((addr >> 18) & 0xF0));
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#endif
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#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
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( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
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#if (( (DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \
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((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1) )
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}
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#endif
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@ -83,18 +83,18 @@
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*/
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/* set default */
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#if !defined( DRXDAPFASI_LONG_ADDR_ALLOWED )
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#if !defined(DRXDAPFASI_LONG_ADDR_ALLOWED)
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#define DRXDAPFASI_LONG_ADDR_ALLOWED 1
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#endif
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/* set default */
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#if !defined( DRXDAPFASI_SHORT_ADDR_ALLOWED )
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#if !defined(DRXDAPFASI_SHORT_ADDR_ALLOWED)
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#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1
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#endif
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/* check */
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#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \
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( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) )
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#if (( DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && \
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(DRXDAPFASI_SHORT_ADDR_ALLOWED == 0) )
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#error At least one of short- or long-addressing format must be allowed.
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*; /* illegal statement to force compiler error */
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#endif
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@ -176,12 +176,12 @@
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*/
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/* set default */
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#if !defined( DRXDAP_MAX_WCHUNKSIZE)
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#if !defined(DRXDAP_MAX_WCHUNKSIZE)
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#define DRXDAP_MAX_WCHUNKSIZE 254
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#endif
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/* check */
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#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) )
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#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
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#if DRXDAP_SINGLE_MASTER
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#define DRXDAP_MAX_WCHUNKSIZE_MIN 3
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#else
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@ -196,7 +196,7 @@
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#endif
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#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN
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#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) )
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#if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 0) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
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#if DRXDAP_SINGLE_MASTER
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#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
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*; /* illegal statement to force compiler error */
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@ -216,7 +216,7 @@
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#endif
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/* set default */
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#if !defined( DRXDAP_MAX_RCHUNKSIZE)
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#if !defined(DRXDAP_MAX_RCHUNKSIZE)
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#define DRXDAP_MAX_RCHUNKSIZE 254
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#endif
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@ -249,13 +249,13 @@ extern "C" {
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#define DRXDAP_FASI_MODEFLAGS 0xC0000000
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#define DRXDAP_FASI_FLAGS 0xF0000000
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#define DRXDAP_FASI_ADDR2BLOCK( addr ) (((addr)>>22)&0x3F)
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#define DRXDAP_FASI_ADDR2BANK( addr ) (((addr)>>16)&0x3F)
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#define DRXDAP_FASI_ADDR2OFFSET( addr ) ((addr)&0x7FFF)
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#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr)>>22)&0x3F)
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#define DRXDAP_FASI_ADDR2BANK(addr) (((addr)>>16)&0x3F)
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#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr)&0x7FFF)
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#define DRXDAP_FASI_SHORT_FORMAT( addr ) (((addr)& 0xFC30FF80)==0)
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#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0)
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#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0)
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#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
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#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
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#define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr) & 0x00008000) != 0)
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#ifdef __cplusplus
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}
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@ -99,15 +99,15 @@ DEFINES
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/*=== MACROS =================================================================*/
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/*============================================================================*/
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#define DRX_ISPOWERDOWNMODE( mode ) ( ( mode == DRX_POWER_MODE_9 ) || \
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( mode == DRX_POWER_MODE_10 ) || \
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( mode == DRX_POWER_MODE_11 ) || \
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( mode == DRX_POWER_MODE_12 ) || \
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( mode == DRX_POWER_MODE_13 ) || \
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( mode == DRX_POWER_MODE_14 ) || \
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( mode == DRX_POWER_MODE_15 ) || \
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( mode == DRX_POWER_MODE_16 ) || \
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( mode == DRX_POWER_DOWN ) )
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#define DRX_ISPOWERDOWNMODE(mode) ( ( mode == DRX_POWER_MODE_9 ) || \
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(mode == DRX_POWER_MODE_10) || \
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(mode == DRX_POWER_MODE_11) || \
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(mode == DRX_POWER_MODE_12) || \
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(mode == DRX_POWER_MODE_13) || \
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(mode == DRX_POWER_MODE_14) || \
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(mode == DRX_POWER_MODE_15) || \
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(mode == DRX_POWER_MODE_16) || \
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(mode == DRX_POWER_DOWN) )
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/*------------------------------------------------------------------------------
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GLOBAL VARIABLES
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@ -148,7 +148,7 @@ FUNCTIONS
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static int
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ScanFunctionDefault(void *scanContext,
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DRXScanCommand_t scanCommand,
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pDRXChannel_t scanChannel, bool * getNextChannel);
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pDRXChannel_t scanChannel, bool *getNextChannel);
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/**
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* \brief Get pointer to scanning function.
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@ -211,7 +211,7 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext)
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* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted.
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*
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*/
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static int ScanWaitForLock(pDRXDemodInstance_t demod, bool * isLocked)
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static int ScanWaitForLock(pDRXDemodInstance_t demod, bool *isLocked)
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{
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bool doneWaiting = false;
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DRXLockStatus_t lockState = DRX_NOT_LOCKED;
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@ -356,7 +356,7 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip)
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static int
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ScanFunctionDefault(void *scanContext,
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DRXScanCommand_t scanCommand,
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pDRXChannel_t scanChannel, bool * getNextChannel)
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pDRXChannel_t scanChannel, bool *getNextChannel)
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{
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pDRXDemodInstance_t demod = NULL;
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int status = DRX_STS_ERROR;
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@ -604,7 +604,7 @@ static int CtrlScanStop(pDRXDemodInstance_t demod)
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static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress)
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{
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pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
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bool * scanReady = (bool *) (NULL);
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bool *scanReady = (bool *) (NULL);
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u16 maxProgress = DRX_SCAN_MAX_PROGRESS;
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u32 numTries = 0;
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u32 i = 0;
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@ -1202,7 +1202,7 @@ CtrlUCode(pDRXDemodInstance_t demod,
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* \retval DRX_STS_INVALID_ARG: Invalid arguments.
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*/
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static int
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CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList)
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CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList)
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{
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static char drxDriverCoreModuleName[] = "Core driver";
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static char drxDriverCoreVersionText[] =
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File diff suppressed because it is too large
Load Diff
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@ -170,7 +170,7 @@ INCLUDE FILES
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#include "drx_driver_version.h"
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//#define DRX_DEBUG
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/* #define DRX_DEBUG */
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#ifdef DRX_DEBUG
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#include <stdio.h>
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#endif
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@ -183,7 +183,7 @@ ENUMS
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DEFINES
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----------------------------------------------------------------------------*/
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#ifndef DRXJ_WAKE_UP_KEY
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#define DRXJ_WAKE_UP_KEY (demod -> myI2CDevAddr -> i2cAddr)
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#define DRXJ_WAKE_UP_KEY (demod->myI2CDevAddr->i2cAddr)
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#endif
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/**
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@ -306,11 +306,11 @@ DEFINES
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#endif
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/* ATV config changed flags */
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#define DRXJ_ATV_CHANGED_COEF ( 0x00000001UL )
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#define DRXJ_ATV_CHANGED_PEAK_FLT ( 0x00000008UL )
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#define DRXJ_ATV_CHANGED_NOISE_FLT ( 0x00000010UL )
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#define DRXJ_ATV_CHANGED_OUTPUT ( 0x00000020UL )
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#define DRXJ_ATV_CHANGED_SIF_ATT ( 0x00000040UL )
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#define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
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#define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
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#define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
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#define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
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#define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
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/* UIO define */
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#define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
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@ -424,7 +424,7 @@ DEFINES
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/**
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* \brief FM Matrix register fix
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*/
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#ifdef AUD_DEM_WR_FM_MATRIX__A
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#ifdef AUD_DEM_WR_FM_MATRIX__A
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#undef AUD_DEM_WR_FM_MATRIX__A
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#endif
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#define AUD_DEM_WR_FM_MATRIX__A 0x105006F
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@ -480,63 +480,63 @@ DEFINES
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#ifdef DRXJDRIVER_DEBUG
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#include <stdio.h>
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#define CHK_ERROR( s ) \
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do{ \
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if ( (s) != DRX_STS_OK ) \
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#define CHK_ERROR(s) \
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do { \
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if ((s) != DRX_STS_OK) \
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{ \
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fprintf(stderr, \
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"ERROR[\n file : %s\n line : %d\n]\n", \
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__FILE__,__LINE__); \
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__FILE__, __LINE__); \
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goto rw_error; }; \
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} \
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while (0 != 0)
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#else
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#define CHK_ERROR( s ) \
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do{ \
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if ( (s) != DRX_STS_OK ) { goto rw_error; } \
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#define CHK_ERROR(s) \
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do { \
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if ((s) != DRX_STS_OK) { goto rw_error; } \
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} while (0 != 0)
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#endif
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#define CHK_ZERO( s ) \
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do{ \
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if ( (s) == 0 ) return DRX_STS_ERROR; \
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#define CHK_ZERO(s) \
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do { \
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if ((s) == 0) return DRX_STS_ERROR; \
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} while (0)
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#define DUMMY_READ() \
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do{ \
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do { \
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u16 dummy; \
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RR16( demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy ); \
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RR16(demod->myI2CDevAddr, SCU_RAM_VERSION_HI__A, &dummy); \
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} while (0)
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#define WR16( dev, addr, val) \
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CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0 ) )
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#define WR16(dev, addr, val) \
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CHK_ERROR(DRXJ_DAP.writeReg16Func( (dev), (addr), (val), 0) )
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|
||||
#define RR16( dev, addr, val) \
|
||||
CHK_ERROR( DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0 ) )
|
||||
#define RR16(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP.readReg16Func( (dev), (addr), (val), 0) )
|
||||
|
||||
#define WR32( dev, addr, val) \
|
||||
CHK_ERROR( DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0 ) )
|
||||
#define WR32(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP.writeReg32Func( (dev), (addr), (val), 0) )
|
||||
|
||||
#define RR32( dev, addr, val) \
|
||||
CHK_ERROR( DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0 ) )
|
||||
#define RR32(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP.readReg32Func( (dev), (addr), (val), 0) )
|
||||
|
||||
#define WRB( dev, addr, len, block ) \
|
||||
CHK_ERROR( DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0 ) )
|
||||
#define WRB(dev, addr, len, block) \
|
||||
CHK_ERROR(DRXJ_DAP.writeBlockFunc( (dev), (addr), (len), (block), 0) )
|
||||
|
||||
#define RRB( dev, addr, len, block ) \
|
||||
CHK_ERROR( DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0 ) )
|
||||
#define RRB(dev, addr, len, block) \
|
||||
CHK_ERROR(DRXJ_DAP.readBlockFunc( (dev), (addr), (len), (block), 0) )
|
||||
|
||||
#define BCWR16( dev, addr, val ) \
|
||||
CHK_ERROR( DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST ) )
|
||||
#define BCWR16(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP.writeReg16Func( (dev), (addr), (val), DRXDAP_FASI_BROADCAST) )
|
||||
|
||||
#define ARR32( dev, addr, val) \
|
||||
CHK_ERROR( DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0 ) )
|
||||
#define ARR32(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP_AtomicReadReg32( (dev), (addr), (val), 0) )
|
||||
|
||||
#define SARR16( dev, addr, val) \
|
||||
CHK_ERROR( DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0 ) )
|
||||
#define SARR16(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP_SCU_AtomicReadReg16( (dev), (addr), (val), 0) )
|
||||
|
||||
#define SAWR16( dev, addr, val) \
|
||||
CHK_ERROR( DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0 ) )
|
||||
#define SAWR16(dev, addr, val) \
|
||||
CHK_ERROR(DRXJ_DAP_SCU_AtomicWriteReg16( (dev), (addr), (val), 0) )
|
||||
|
||||
/**
|
||||
* This macro is used to create byte arrays for block writes.
|
||||
|
|
@ -544,14 +544,14 @@ DEFINES
|
|||
* The macro takes care of the required byte order in a 16 bits word.
|
||||
* x -> lowbyte(x), highbyte(x)
|
||||
*/
|
||||
#define DRXJ_16TO8( x ) ((u8) (((u16)x) &0xFF)), \
|
||||
#define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
|
||||
((u8)((((u16)x)>>8)&0xFF))
|
||||
/**
|
||||
* This macro is used to convert byte array to 16 bit register value for block read.
|
||||
* Block read speed up I2C traffic between host and demod.
|
||||
* The macro takes care of the required byte order in a 16 bits word.
|
||||
*/
|
||||
#define DRXJ_8TO16( x ) ((u16) (x[0] | (x[1] << 8)))
|
||||
#define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
|
||||
|
||||
/*============================================================================*/
|
||||
/*=== MISC DEFINES ===========================================================*/
|
||||
|
|
@ -570,18 +570,18 @@ DEFINES
|
|||
/*=== STANDARD RELATED MACROS ================================================*/
|
||||
/*============================================================================*/
|
||||
|
||||
#define DRXJ_ISATVSTD( std ) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \
|
||||
( std == DRX_STANDARD_PAL_SECAM_DK ) || \
|
||||
( std == DRX_STANDARD_PAL_SECAM_I ) || \
|
||||
( std == DRX_STANDARD_PAL_SECAM_L ) || \
|
||||
( std == DRX_STANDARD_PAL_SECAM_LP ) || \
|
||||
( std == DRX_STANDARD_NTSC ) || \
|
||||
( std == DRX_STANDARD_FM ) )
|
||||
#define DRXJ_ISATVSTD(std) ( ( std == DRX_STANDARD_PAL_SECAM_BG ) || \
|
||||
(std == DRX_STANDARD_PAL_SECAM_DK) || \
|
||||
(std == DRX_STANDARD_PAL_SECAM_I) || \
|
||||
(std == DRX_STANDARD_PAL_SECAM_L) || \
|
||||
(std == DRX_STANDARD_PAL_SECAM_LP) || \
|
||||
(std == DRX_STANDARD_NTSC) || \
|
||||
(std == DRX_STANDARD_FM) )
|
||||
|
||||
#define DRXJ_ISQAMSTD( std ) ( ( std == DRX_STANDARD_ITU_A ) || \
|
||||
( std == DRX_STANDARD_ITU_B ) || \
|
||||
( std == DRX_STANDARD_ITU_C ) || \
|
||||
( std == DRX_STANDARD_ITU_D ))
|
||||
#define DRXJ_ISQAMSTD(std) ( ( std == DRX_STANDARD_ITU_A ) || \
|
||||
(std == DRX_STANDARD_ITU_B) || \
|
||||
(std == DRX_STANDARD_ITU_C) || \
|
||||
(std == DRX_STANDARD_ITU_D))
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
STATIC VARIABLES
|
||||
|
|
@ -1224,7 +1224,7 @@ CtrlUCodeUpload(pDRXDemodInstance_t demod,
|
|||
*
|
||||
*/
|
||||
|
||||
#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof (u32) * 8 - 1))) != 0)
|
||||
#define DRX_IS_BOOTH_NEGATIVE(__a) (((__a) & (1 << (sizeof(u32) * 8 - 1))) != 0)
|
||||
|
||||
static void Mult32(u32 a, u32 b, u32 *h, u32 *l)
|
||||
{
|
||||
|
|
@ -1683,7 +1683,7 @@ static const u16 NicamPrescTableVal[43] =
|
|||
TODO: check ignoring single/multimaster is ok for AUD access ?
|
||||
*/
|
||||
|
||||
#define DRXJ_ISAUDWRITE( addr ) (((((addr)>>16)&1)==1)?true:false)
|
||||
#define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1)?true:false)
|
||||
#define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
|
||||
/*============================================================================*/
|
||||
|
||||
|
|
@ -1755,7 +1755,7 @@ static int DRXJ_DAP_ReadModifyWriteReg8(struct i2c_device_addr *devAddr,
|
|||
|
||||
/* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
|
||||
See comments DRXJ_DAP_ReadModifyWriteReg16 */
|
||||
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED == 0 )
|
||||
#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
|
||||
static int DRXJ_DAP_RMWriteReg16Short(struct i2c_device_addr *devAddr,
|
||||
DRXaddr_t waddr,
|
||||
DRXaddr_t raddr,
|
||||
|
|
@ -1803,7 +1803,7 @@ static int DRXJ_DAP_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
|
|||
/* TODO: correct short/long addressing format decision,
|
||||
now long format has higher prio then short because short also
|
||||
needs virt bnks (not impl yet) for certain audio registers */
|
||||
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
|
||||
#if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
|
||||
return drxDapFASIFunct_g.readModifyWriteReg16Func(devAddr,
|
||||
waddr,
|
||||
raddr, wdata, rdata);
|
||||
|
|
@ -3492,7 +3492,7 @@ static int CtrlGetUIOCfg(pDRXDemodInstance_t demod, pDRXUIOCfg_t UIOCfg)
|
|||
|
||||
pDRXJData_t extAttr = (pDRXJData_t) NULL;
|
||||
pDRXUIOMode_t UIOMode[4] = { NULL };
|
||||
bool * UIOAvailable[4] = { NULL };
|
||||
bool *UIOAvailable[4] = { NULL };
|
||||
|
||||
extAttr = demod->myExtAttr;
|
||||
|
||||
|
|
@ -3823,7 +3823,7 @@ static int CtrlUIORead(pDRXDemodInstance_t demod, pDRXUIOData_t UIOData)
|
|||
|
||||
*/
|
||||
static int
|
||||
CtrlI2CBridge(pDRXDemodInstance_t demod, bool * bridgeClosed)
|
||||
CtrlI2CBridge(pDRXDemodInstance_t demod, bool *bridgeClosed)
|
||||
{
|
||||
DRXJHiCmd_t hiCmd;
|
||||
u16 result = 0;
|
||||
|
|
@ -3908,7 +3908,7 @@ CtrlSetCfgSmartAnt(pDRXDemodInstance_t demod, pDRXJCfgSmartAnt_t smartAnt)
|
|||
struct i2c_device_addr *devAddr = NULL;
|
||||
u16 data = 0;
|
||||
u32 startTime = 0;
|
||||
static bool bitInverted = false;
|
||||
static bool bitInverted;
|
||||
|
||||
devAddr = demod->myI2CDevAddr;
|
||||
extAttr = (pDRXJData_t) demod->myExtAttr;
|
||||
|
|
@ -4356,7 +4356,7 @@ CtrlSetCfgATVOutput(pDRXDemodInstance_t demod, pDRXJCfgAtvOutput_t outputCfg);
|
|||
* \return int.
|
||||
*/
|
||||
static int
|
||||
CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enable)
|
||||
CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enable)
|
||||
{
|
||||
pDRXJData_t extAttr = (pDRXJData_t) NULL;
|
||||
struct i2c_device_addr *devAddr = (struct i2c_device_addr *) NULL;
|
||||
|
|
@ -4482,7 +4482,7 @@ CtrlSetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enable)
|
|||
* \return int.
|
||||
*/
|
||||
static int
|
||||
CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool * enabled)
|
||||
CtrlGetCfgPdrSafeMode(pDRXDemodInstance_t demod, bool *enabled)
|
||||
{
|
||||
pDRXJData_t extAttr = (pDRXJData_t) NULL;
|
||||
|
||||
|
|
@ -4926,8 +4926,8 @@ static int GetSigStrength(pDRXDemodInstance_t demod, u16 *sigStrength)
|
|||
#ifdef DRXJ_SIGNAL_ACCUM_ERR
|
||||
static int GetAccPktErr(pDRXDemodInstance_t demod, u16 *packetErr)
|
||||
{
|
||||
static u16 pktErr = 0;
|
||||
static u16 lastPktErr = 0;
|
||||
static u16 pktErr;
|
||||
static u16 lastPktErr;
|
||||
u16 data = 0;
|
||||
pDRXJData_t extAttr = NULL;
|
||||
struct i2c_device_addr *devAddr = NULL;
|
||||
|
|
@ -5046,7 +5046,7 @@ static int GetCTLFreqOffset(pDRXDemodInstance_t demod, s32 *CTLFreq)
|
|||
|
||||
/* both registers are sign extended */
|
||||
nominalFrequency = extAttr->iqmFsRateOfs;
|
||||
ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) & currentFrequency);
|
||||
ARR32(devAddr, IQM_FS_RATE_LO__A, (u32 *) ¤tFrequency);
|
||||
|
||||
if (extAttr->posImage == true) {
|
||||
/* negative image */
|
||||
|
|
@ -6174,7 +6174,7 @@ static int GetVSBpostViterbiBer(struct i2c_device_addr *devAddr, u32 *ber)
|
|||
* \brief Get the values of ber in VSB mode
|
||||
* \return Error code
|
||||
*/
|
||||
static int GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 * ber)
|
||||
static int GetVSBpreViterbiBer(struct i2c_device_addr *devAddr, u32 *ber)
|
||||
{
|
||||
u16 data = 0;
|
||||
|
||||
|
|
@ -8108,7 +8108,7 @@ CtrlGetQAMConstel(pDRXDemodInstance_t demod, pDRXComplex_t complexNr)
|
|||
WR16(devAddr, QAM_SL_COMM_MB__A, qamSlCommMb);
|
||||
|
||||
/* Enable MB grabber in the FEC OC */
|
||||
fecOcOcrMode = ( /* output select: observe bus */
|
||||
fecOcOcrMode = (/* output select: observe bus */
|
||||
(FEC_OC_OCR_MODE_MB_SELECT__M &
|
||||
(0x0 << FEC_OC_OCR_MODE_MB_SELECT__B)) |
|
||||
/* grabber enable: on */
|
||||
|
|
@ -8451,10 +8451,10 @@ CtrlSetCfgAtvEquCoef(pDRXDemodInstance_t demod, pDRXJCfgAtvEquCoef_t coef)
|
|||
(coef->coef1 > (ATV_TOP_EQU1_EQU_C1__M / 2)) ||
|
||||
(coef->coef2 > (ATV_TOP_EQU2_EQU_C2__M / 2)) ||
|
||||
(coef->coef3 > (ATV_TOP_EQU3_EQU_C3__M / 2)) ||
|
||||
(coef->coef0 < ((s16) ~ (ATV_TOP_EQU0_EQU_C0__M >> 1))) ||
|
||||
(coef->coef1 < ((s16) ~ (ATV_TOP_EQU1_EQU_C1__M >> 1))) ||
|
||||
(coef->coef2 < ((s16) ~ (ATV_TOP_EQU2_EQU_C2__M >> 1))) ||
|
||||
(coef->coef3 < ((s16) ~ (ATV_TOP_EQU3_EQU_C3__M >> 1)))) {
|
||||
(coef->coef0 < ((s16) ~(ATV_TOP_EQU0_EQU_C0__M >> 1))) ||
|
||||
(coef->coef1 < ((s16) ~(ATV_TOP_EQU1_EQU_C1__M >> 1))) ||
|
||||
(coef->coef2 < ((s16) ~(ATV_TOP_EQU2_EQU_C2__M >> 1))) ||
|
||||
(coef->coef3 < ((s16) ~(ATV_TOP_EQU3_EQU_C3__M >> 1)))) {
|
||||
return (DRX_STS_INVALID_ARG);
|
||||
}
|
||||
|
||||
|
|
@ -10231,7 +10231,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume)
|
|||
RR16(devAddr, AUD_DSP_WR_VOLUME__A, &wVolume);
|
||||
|
||||
/* clear the volume mask */
|
||||
wVolume &= (u16) ~ AUD_DSP_WR_VOLUME_VOL_MAIN__M;
|
||||
wVolume &= (u16) ~AUD_DSP_WR_VOLUME_VOL_MAIN__M;
|
||||
if (volume->mute == true) {
|
||||
/* mute */
|
||||
/* mute overrules volume */
|
||||
|
|
@ -10248,8 +10248,8 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume)
|
|||
RR16(devAddr, AUD_DSP_WR_AVC__A, &wAVC);
|
||||
|
||||
/* clear masks that require writing */
|
||||
wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_ON__M;
|
||||
wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_DECAY__M;
|
||||
wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_ON__M;
|
||||
wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_DECAY__M;
|
||||
|
||||
if (volume->avcMode == DRX_AUD_AVC_OFF) {
|
||||
wAVC |= (AUD_DSP_WR_AVC_AVC_ON_OFF);
|
||||
|
|
@ -10277,7 +10277,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume)
|
|||
}
|
||||
|
||||
/* max attenuation */
|
||||
wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_MAX_ATT__M;
|
||||
wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_ATT__M;
|
||||
switch (volume->avcMaxAtten) {
|
||||
case DRX_AUD_AVC_MAX_ATTEN_12DB:
|
||||
wAVC |= AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB;
|
||||
|
|
@ -10293,7 +10293,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume)
|
|||
}
|
||||
|
||||
/* max gain */
|
||||
wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_MAX_GAIN__M;
|
||||
wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_MAX_GAIN__M;
|
||||
switch (volume->avcMaxGain) {
|
||||
case DRX_AUD_AVC_MAX_GAIN_0DB:
|
||||
wAVC |= AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB;
|
||||
|
|
@ -10313,7 +10313,7 @@ AUDCtrlSetCfgVolume(pDRXDemodInstance_t demod, pDRXCfgAudVolume_t volume)
|
|||
return DRX_STS_INVALID_ARG;
|
||||
}
|
||||
|
||||
wAVC &= (u16) ~ AUD_DSP_WR_AVC_AVC_REF_LEV__M;
|
||||
wAVC &= (u16) ~AUD_DSP_WR_AVC_AVC_REF_LEV__M;
|
||||
wAVC |= (u16) (volume->avcRefLevel << AUD_DSP_WR_AVC_AVC_REF_LEV__B);
|
||||
|
||||
WR16(devAddr, AUD_DSP_WR_AVC__A, wAVC);
|
||||
|
|
@ -10465,7 +10465,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output)
|
|||
RR16(devAddr, AUD_DEM_RAM_I2S_CONFIG2__A, &wI2SConfig);
|
||||
|
||||
/* I2S mode */
|
||||
wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M;
|
||||
wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M;
|
||||
|
||||
switch (output->mode) {
|
||||
case DRX_I2S_MODE_MASTER:
|
||||
|
|
@ -10479,7 +10479,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output)
|
|||
}
|
||||
|
||||
/* I2S format */
|
||||
wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M;
|
||||
wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M;
|
||||
|
||||
switch (output->format) {
|
||||
case DRX_I2S_FORMAT_WS_ADVANCED:
|
||||
|
|
@ -10493,7 +10493,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output)
|
|||
}
|
||||
|
||||
/* I2S word length */
|
||||
wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M;
|
||||
wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M;
|
||||
|
||||
switch (output->wordLength) {
|
||||
case DRX_I2S_WORDLENGTH_16:
|
||||
|
|
@ -10507,7 +10507,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output)
|
|||
}
|
||||
|
||||
/* I2S polarity */
|
||||
wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M;
|
||||
wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M;
|
||||
switch (output->polarity) {
|
||||
case DRX_I2S_POLARITY_LEFT:
|
||||
wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH;
|
||||
|
|
@ -10520,7 +10520,7 @@ AUDCtrlSetCfgOutputI2S(pDRXDemodInstance_t demod, pDRXCfgI2SOutput_t output)
|
|||
}
|
||||
|
||||
/* I2S output enabled */
|
||||
wI2SConfig &= (u16) ~ AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M;
|
||||
wI2SConfig &= (u16) ~AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M;
|
||||
if (output->outputEnable == true) {
|
||||
wI2SConfig |= AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE;
|
||||
} else {
|
||||
|
|
@ -10676,8 +10676,8 @@ AUDCtrSetlCfgAutoSound(pDRXDemodInstance_t demod,
|
|||
|
||||
wModus = rModus;
|
||||
/* clear ASS & ASC bits */
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_ASS__M;
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_ASS__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M;
|
||||
|
||||
switch (*autoSound) {
|
||||
case DRX_AUD_AUTO_SOUND_OFF:
|
||||
|
|
@ -10936,7 +10936,7 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers)
|
|||
CHK_ERROR(AUDGetModus(demod, &rModus));
|
||||
|
||||
wModus = rModus;
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_CM_A__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_A__M;
|
||||
/* Behaviour of primary audio channel */
|
||||
switch (carriers->a.opt) {
|
||||
case DRX_NO_CARRIER_MUTE:
|
||||
|
|
@ -10951,7 +10951,7 @@ AUDCtrlSetCfgCarrier(pDRXDemodInstance_t demod, pDRXCfgAudCarriers_t carriers)
|
|||
}
|
||||
|
||||
/* Behaviour of secondary audio channel */
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_CM_B__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_CM_B__M;
|
||||
switch (carriers->b.opt) {
|
||||
case DRX_NO_CARRIER_MUTE:
|
||||
wModus |= AUD_DEM_WR_MODUS_MOD_CM_B_MUTE;
|
||||
|
|
@ -11122,7 +11122,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer)
|
|||
|
||||
/* Source Selctor */
|
||||
RR16(devAddr, AUD_DSP_WR_SRC_I2S_MATR__A, &srcI2SMatr);
|
||||
srcI2SMatr &= (u16) ~ AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M;
|
||||
srcI2SMatr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M;
|
||||
|
||||
switch (mixer->sourceI2S) {
|
||||
case DRX_AUD_SRC_MONO:
|
||||
|
|
@ -11142,7 +11142,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer)
|
|||
}
|
||||
|
||||
/* Matrix */
|
||||
srcI2SMatr &= (u16) ~ AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M;
|
||||
srcI2SMatr &= (u16) ~AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M;
|
||||
switch (mixer->matrixI2S) {
|
||||
case DRX_AUD_I2S_MATRIX_MONO:
|
||||
srcI2SMatr |= AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO;
|
||||
|
|
@ -11164,7 +11164,7 @@ AUDCtrlSetCfgMixer(pDRXDemodInstance_t demod, pDRXCfgAudMixer_t mixer)
|
|||
|
||||
/* FM Matrix */
|
||||
RR16(devAddr, AUD_DEM_WR_FM_MATRIX__A, &fmMatr);
|
||||
fmMatr &= (u16) ~ AUD_DEM_WR_FM_MATRIX__M;
|
||||
fmMatr &= (u16) ~AUD_DEM_WR_FM_MATRIX__M;
|
||||
switch (mixer->matrixFm) {
|
||||
case DRX_AUD_FM_MATRIX_NO_MATRIX:
|
||||
fmMatr |= AUD_DEM_WR_FM_MATRIX_NO_MATRIX;
|
||||
|
|
@ -11230,7 +11230,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync)
|
|||
/* audio/video synchronisation */
|
||||
RR16(devAddr, AUD_DSP_WR_AV_SYNC__A, &wAudVidSync);
|
||||
|
||||
wAudVidSync &= (u16) ~ AUD_DSP_WR_AV_SYNC_AV_ON__M;
|
||||
wAudVidSync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_ON__M;
|
||||
|
||||
if (*avSync == DRX_AUD_AVSYNC_OFF) {
|
||||
wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE;
|
||||
|
|
@ -11238,7 +11238,7 @@ AUDCtrlSetCfgAVSync(pDRXDemodInstance_t demod, pDRXCfgAudAVSync_t avSync)
|
|||
wAudVidSync |= AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE;
|
||||
}
|
||||
|
||||
wAudVidSync &= (u16) ~ AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M;
|
||||
wAudVidSync &= (u16) ~AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M;
|
||||
|
||||
switch (*avSync) {
|
||||
case DRX_AUD_AVSYNC_NTSC:
|
||||
|
|
@ -11389,7 +11389,7 @@ AUDCtrlSetCfgDev(pDRXDemodInstance_t demod, pDRXCfgAudDeviation_t dev)
|
|||
|
||||
wModus = rModus;
|
||||
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_HDEV_A__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_HDEV_A__M;
|
||||
|
||||
switch (*dev) {
|
||||
case DRX_AUD_DEVIATION_NORMAL:
|
||||
|
|
@ -11745,7 +11745,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard)
|
|||
/* we need the current standard here */
|
||||
currentStandard = extAttr->standard;
|
||||
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_6_5MHZ__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_6_5MHZ__M;
|
||||
|
||||
if ((currentStandard == DRX_STANDARD_PAL_SECAM_L) ||
|
||||
(currentStandard == DRX_STANDARD_PAL_SECAM_LP)) {
|
||||
|
|
@ -11754,7 +11754,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard)
|
|||
wModus |= (AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K);
|
||||
}
|
||||
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_4_5MHZ__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_4_5MHZ__M;
|
||||
if (currentStandard == DRX_STANDARD_NTSC) {
|
||||
wModus |= (AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC);
|
||||
|
||||
|
|
@ -11765,7 +11765,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard)
|
|||
|
||||
}
|
||||
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_FMRADIO__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_FMRADIO__M;
|
||||
|
||||
/* just get hardcoded deemphasis and activate here */
|
||||
if (extAttr->audData.deemph == DRX_AUD_FM_DEEMPH_50US) {
|
||||
|
|
@ -11774,7 +11774,7 @@ AUDCtrlSetStandard(pDRXDemodInstance_t demod, pDRXAudStandard_t standard)
|
|||
wModus |= (AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U);
|
||||
}
|
||||
|
||||
wModus &= (u16) ~ AUD_DEM_WR_MODUS_MOD_BTSC__M;
|
||||
wModus &= (u16) ~AUD_DEM_WR_MODUS_MOD_BTSC__M;
|
||||
if (extAttr->audData.btscDetect == DRX_BTSC_STEREO) {
|
||||
wModus |= (AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO);
|
||||
} else { /* DRX_BTSC_MONO_AND_SAP */
|
||||
|
|
@ -12464,9 +12464,9 @@ static int SetOrxNsuAox(pDRXDemodInstance_t demod, bool active)
|
|||
*/
|
||||
|
||||
/* Nyquist filter impulse response */
|
||||
#define IMPULSE_COSINE_ALPHA_0_3 {-3,-4,-1, 6,10, 7,-5,-20,-25,-10,29,79,123,140} /*sqrt raised-cosine filter with alpha=0.3 */
|
||||
#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0,-2,-2, 2, 5, 2,-10,-20,-14,20,74,125,145} /*sqrt raised-cosine filter with alpha=0.5 */
|
||||
#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0,-7,-15,-16, 0,34,77,114,128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
|
||||
#define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
|
||||
#define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
|
||||
#define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
|
||||
|
||||
/* Coefficients for the nyquist fitler (total: 27 taps) */
|
||||
#define NYQFILTERLEN 27
|
||||
|
|
@ -14122,7 +14122,7 @@ CtrlPowerMode(pDRXDemodInstance_t demod, pDRXPowerMode_t mode)
|
|||
*
|
||||
*/
|
||||
static int
|
||||
CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList)
|
||||
CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList)
|
||||
{
|
||||
pDRXJData_t extAttr = (pDRXJData_t) (NULL);
|
||||
struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL);
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ extern "C" {
|
|||
/* Multi master mode and short addr format only will not work.
|
||||
RMW, CRC reset, broadcast and switching back to single master mode
|
||||
cannot be done with short addr only in multi master mode. */
|
||||
#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0))
|
||||
#if ((DRXDAP_SINGLE_MASTER == 0) && (DRXDAPFASI_LONG_ADDR_ALLOWED == 0))
|
||||
#error "Multi master mode and short addressing only is an illegal combination"
|
||||
*; /* Generate a fatal compiler error to make sure it stops here,
|
||||
this is necesarry because not all compilers stop after a #error. */
|
||||
|
|
@ -590,7 +590,7 @@ Access MACROS
|
|||
*
|
||||
*/
|
||||
|
||||
#define DRXJ_ATTR_BTSC_DETECT( d ) \
|
||||
#define DRXJ_ATTR_BTSC_DETECT(d) \
|
||||
(((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect)
|
||||
|
||||
/**
|
||||
|
|
@ -604,15 +604,15 @@ Access MACROS
|
|||
* substituted by "direct-access-inline-code" or a function call.
|
||||
*
|
||||
*/
|
||||
#define DRXJ_GET_BTSC_DETECT( d, x ) \
|
||||
#define DRXJ_GET_BTSC_DETECT(d, x) \
|
||||
do { \
|
||||
(x) = DRXJ_ATTR_BTSC_DETECT(( d ); \
|
||||
} while(0)
|
||||
(x) = DRXJ_ATTR_BTSC_DETECT((d); \
|
||||
} while (0)
|
||||
|
||||
#define DRXJ_SET_BTSC_DETECT( d, x ) \
|
||||
#define DRXJ_SET_BTSC_DETECT(d, x) \
|
||||
do { \
|
||||
DRXJ_ATTR_BTSC_DETECT( d ) = (x); \
|
||||
} while(0)
|
||||
DRXJ_ATTR_BTSC_DETECT(d) = (x); \
|
||||
} while (0)
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
DEFINES
|
||||
|
|
@ -704,12 +704,12 @@ DEFINES
|
|||
|
||||
/* Convert OOB lock status to string */
|
||||
#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \
|
||||
( x == DRX_NEVER_LOCK ) ? "Never" : \
|
||||
( x == DRX_NOT_LOCKED ) ? "No" : \
|
||||
( x == DRX_LOCKED ) ? "Locked" : \
|
||||
( x == DRX_LOCK_STATE_1 ) ? "AGC lock" : \
|
||||
( x == DRX_LOCK_STATE_2 ) ? "sync lock" : \
|
||||
"(Invalid)" )
|
||||
(x == DRX_NEVER_LOCK) ? "Never" : \
|
||||
(x == DRX_NOT_LOCKED) ? "No" : \
|
||||
(x == DRX_LOCKED) ? "Locked" : \
|
||||
(x == DRX_LOCK_STATE_1) ? "AGC lock" : \
|
||||
(x == DRX_LOCK_STATE_2) ? "sync lock" : \
|
||||
"(Invalid)")
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
ENUM
|
||||
|
|
|
|||
Loading…
Reference in New Issue