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dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
Add the binding for the TLMM pinctrl block found in the SM8150 platform. Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org> [vkoul: add missing nodes of gpio range and reserved rewrote function names and order them] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20190702105045.27646-3-vkoul@kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Prasad Sodagudi
Linus Walleij
parent
80327437e3
commit
7f1fee22a2
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Qualcomm SM8150 TLMM block
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This binding describes the Top Level Mode Multiplexer block found in the
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QCS404 platform.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,sm8150-pinctrl"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the north, south, west
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and east TLMM tiles.
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- reg-names:
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Usage: required
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Value type: <prop-encoded-array>
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Defintiion: names for the cells of reg, must contain "north", "south"
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"west" and "east".
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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- interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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- gpio-ranges:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: see ../gpio/gpio.txt
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- gpio-reserved-ranges:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: see ../gpio/gpio.txt
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode.
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Valid pins are:
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gpio0-gpio149
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Supports mux, bias and drive-strength
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sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
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sdc2_data sdc1_rclk
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Supports bias and drive-strength
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ufs_reset
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Supports bias and drive-strength
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values are:
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adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
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atest_char0, atest_char1, atest_char2, atest_char3,
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audio_ref, atest_usb1, atest_usb2, atest_usb10,
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atest_usb11, atest_usb12, atest_usb13, atest_usb20,
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atest_usb21, atest_usb22, atest_usb2, atest_usb23,
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btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
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cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
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ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
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emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
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hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
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lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
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mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
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pa_indicator, pci_e0, phase_flag, pll_bypassnl,
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pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
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prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
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qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
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qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
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qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
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qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
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sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
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tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
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tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
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usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
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wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configued as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configued as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configued as pull up.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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Not valid for sdc pins.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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Not valid for sdc pins.
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- drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
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Example:
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tlmm: pinctrl@3000000 {
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compatible = "qcom,sm8150-pinctrl";
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reg = <0x03100000 0x300000>,
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<0x03500000 0x300000>,
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<0x03900000 0x300000>,
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<0x03D00000 0x300000>;
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reg-names = "west", "east", "north", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 175>;
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gpio-reserved-ranges = <0 4>, <126 4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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