bnx2x: Eliminate duplicate barriers on weakly-ordered archs

Code includes wmb() followed by writel(). writel() already has a
barrier on some architectures like arm64.

This ends up CPU observing two barriers back to back before executing
the register write.

Since code already has an explicit barrier call, changing writel() to
writel_relaxed().

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sinan Kaya 2018-03-25 10:39:18 -04:00 committed by David S. Miller
parent edd874235a
commit 7f883c774e
6 changed files with 17 additions and 11 deletions

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@ -166,6 +166,12 @@ do { \
#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
#define REG_WR_RELAXED(bp, offset, val) \
writel_relaxed((u32)val, REG_ADDR(bp, offset))
#define REG_WR16_RELAXED(bp, offset, val) \
writew_relaxed((u16)val, REG_ADDR(bp, offset))
#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
@ -758,10 +764,8 @@ struct bnx2x_fastpath {
#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
#error "Min DB doorbell stride is 8" #error "Min DB doorbell stride is 8"
#endif #endif
#define DOORBELL(bp, cid, val) \ #define DOORBELL_RELAXED(bp, cid, val) \
do { \ writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
} while (0)
/* TX CSUM helpers */ /* TX CSUM helpers */
#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \

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@ -4156,7 +4156,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
/* make sure descriptor update is observed by HW */ /* make sure descriptor update is observed by HW */
wmb(); wmb();
DOORBELL(bp, txdata->cid, txdata->tx_db.raw); DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
mmiowb(); mmiowb();

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@ -522,8 +522,8 @@ static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
wmb(); wmb();
for (i = 0; i < sizeof(rx_prods)/4; i++) for (i = 0; i < sizeof(rx_prods)/4; i++)
REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, REG_WR_RELAXED(bp, fp->ustorm_rx_prods_offset + i * 4,
((u32 *)&rx_prods)[i]); ((u32 *)&rx_prods)[i]);
mmiowb(); /* keep prod updates ordered */ mmiowb(); /* keep prod updates ordered */

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@ -2593,7 +2593,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
txdata->tx_db.data.prod += 2; txdata->tx_db.data.prod += 2;
/* make sure descriptor update is observed by the HW */ /* make sure descriptor update is observed by the HW */
wmb(); wmb();
DOORBELL(bp, txdata->cid, txdata->tx_db.raw); DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
mmiowb(); mmiowb();
barrier(); barrier();

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@ -3817,8 +3817,8 @@ static void bnx2x_sp_prod_update(struct bnx2x *bp)
*/ */
mb(); mb();
REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
bp->spq_prod_idx); bp->spq_prod_idx);
mmiowb(); mmiowb();
} }

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@ -170,7 +170,9 @@ static int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping)
wmb(); wmb();
/* Trigger the PF FW */ /* Trigger the PF FW */
writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid); writeb_relaxed(1, &zone_data->trigger.vf_pf_channel.addr_valid);
mmiowb();
/* Wait for PF to complete */ /* Wait for PF to complete */
while ((tout >= 0) && (!*done)) { while ((tout >= 0) && (!*done)) {