mirror of https://gitee.com/openkylin/linux.git
Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next
* clk-hisi-usb: clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC * clk-silent-bulk: clk: bulk: silently error out on EPROBE_DEFER * clk-mtk-hdmi: clk: mediatek: correct the clocks for MT2701 HDMI PHY module * clk-mtk-mali: clk: mediatek: add g3dsys support for MT2701 and MT7623 dt-bindings: reset: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add entry for Mali-450 node to refer dt-bindings: clock: mediatek: add g3dsys bindings * clk-imx6ul-ccosr: clk: imx: Add new clo01 and clo2 controlled by CCOSR
This commit is contained in:
Stephen Boyd
commit
7fa50aa559
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@ -0,0 +1,30 @@
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MediaTek g3dsys controller
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============================
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The MediaTek g3dsys controller provides various clocks and reset controller to
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the GPU.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-g3dsys", "syscon":
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for MT2701 SoC
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- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
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for MT7623 SoC
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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The g3dsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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g3dsys: clock-controller@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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"syscon";
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reg = <0 0x13000000 0 0x200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -42,6 +42,7 @@ int __must_check clk_bulk_get(struct device *dev, int num_clks,
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clks[i].clk = clk_get(dev, clks[i].id);
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if (IS_ERR(clks[i].clk)) {
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ret = PTR_ERR(clks[i].clk);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "Failed to get clk '%s': %d\n",
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clks[i].id, ret);
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clks[i].clk = NULL;
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@ -186,6 +186,23 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
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{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
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CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
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/* USB3 */
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{ HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
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{ HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
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{ HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
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{ HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
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{ HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
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{ HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
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{ HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
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{ HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
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CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
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};
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static struct hisi_clock_data *hi3798cv200_clk_register(
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@ -68,6 +68,13 @@ static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "
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static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
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static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
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static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dummy", "dummy",
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"dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
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static const char *cko2_sels[] = { "dummy", "dummy", "dummy", "usdhc1", "dummy", "dummy", "ecspi_root", "dummy",
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"dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "osc", "dummy",
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"dummy", "usdhc2", "sai1", "sai2", "sai3", "dummy", "dummy", "can_root",
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"dummy", "dummy", "dummy", "dummy", "uart_serial", "spdif", "dummy", "dummy", };
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static const char *cko_sels[] = { "cko1", "cko2", };
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static struct clk *clks[IMX6UL_CLK_END];
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static struct clk_onecell_data clk_data;
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@ -273,6 +280,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
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clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
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clks[IMX6UL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
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clks[IMX6UL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
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clks[IMX6UL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
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clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
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clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
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@ -316,6 +327,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3);
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clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
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clks[IMX6UL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
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clks[IMX6UL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
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clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
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clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
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clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
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@ -445,6 +459,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
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clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30);
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/* CCOSR */
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clks[IMX6UL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
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clks[IMX6UL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
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/* mask handshake of mmdc */
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writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
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@ -60,6 +60,12 @@ config COMMON_CLK_MT2701_AUDSYS
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---help---
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This driver supports Mediatek MT2701 audsys clocks.
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config COMMON_CLK_MT2701_G3DSYS
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bool "Clock driver for MediaTek MT2701 g3dsys"
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depends on COMMON_CLK_MT2701
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---help---
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This driver supports MediaTek MT2701 g3dsys clocks.
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config COMMON_CLK_MT2712
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bool "Clock driver for MediaTek MT2712"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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@ -9,6 +9,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
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obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
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obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
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obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
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obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
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obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
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obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
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obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
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@ -0,0 +1,95 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt2701-clk.h>
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#define GATE_G3D(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &g3d_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate_regs g3d_cg_regs = {
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.sta_ofs = 0x0,
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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};
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static const struct mtk_gate g3d_clks[] = {
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GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
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};
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static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
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mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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mtk_register_reset_controller(node, 1, 0xc);
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return r;
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}
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static const struct of_device_id of_match_clk_mt2701_g3d[] = {
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{
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.compatible = "mediatek,mt2701-g3dsys",
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.data = clk_mt2701_g3dsys_init,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt2701_g3d_probe(struct platform_device *pdev)
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{
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int (*clk_init)(struct platform_device *);
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int r;
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clk_init = of_device_get_match_data(&pdev->dev);
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if (!clk_init)
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return -EINVAL;
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r = clk_init(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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return r;
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}
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static struct platform_driver clk_mt2701_g3d_drv = {
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.probe = clk_mt2701_g3d_probe,
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.driver = {
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.name = "clk-mt2701-g3d",
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.of_match_table = of_match_clk_mt2701_g3d,
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},
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};
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builtin_platform_driver(clk_mt2701_g3d_drv);
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|
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@ -46,8 +46,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
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340 * MHZ),
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FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
|
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340 * MHZ),
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FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
|
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300 * MHZ),
|
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FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
|
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27 * MHZ),
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FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
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|
|
@ -977,6 +975,10 @@ static const struct mtk_pll_data apmixed_plls[] = {
|
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21, 0x2d0, 4, 0x0, 0x2d4, 0),
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};
|
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|
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static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
|
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FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
|
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};
|
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|
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static int mtk_apmixedsys_init(struct platform_device *pdev)
|
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{
|
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struct clk_onecell_data *clk_data;
|
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|
|
@ -988,6 +990,8 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
|
|||
|
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mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
|
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clk_data);
|
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mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
|
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clk_data);
|
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|
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
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}
|
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|
|
|
|||
|
|
@ -62,6 +62,14 @@
|
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#define HISTB_USB2_PHY1_REF_CLK 40
|
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#define HISTB_USB2_PHY2_REF_CLK 41
|
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#define HISTB_COMBPHY0_CLK 42
|
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#define HISTB_USB3_BUS_CLK 43
|
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#define HISTB_USB3_UTMI_CLK 44
|
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#define HISTB_USB3_PIPE_CLK 45
|
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#define HISTB_USB3_SUSPEND_CLK 46
|
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#define HISTB_USB3_BUS_CLK1 47
|
||||
#define HISTB_USB3_UTMI_CLK1 48
|
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#define HISTB_USB3_PIPE_CLK1 49
|
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#define HISTB_USB3_SUSPEND_CLK1 50
|
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|
||||
/* clocks provided by mcu CRG */
|
||||
#define HISTB_MCE_CLK 1
|
||||
|
|
|
|||
|
|
@ -235,20 +235,27 @@
|
|||
#define IMX6UL_CLK_CSI_PODF 222
|
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#define IMX6UL_CLK_PLL3_120M 223
|
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#define IMX6UL_CLK_KPP 224
|
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#define IMX6UL_CLK_CKO1_SEL 225
|
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#define IMX6UL_CLK_CKO1_PODF 226
|
||||
#define IMX6UL_CLK_CKO1 227
|
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#define IMX6UL_CLK_CKO2_SEL 228
|
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#define IMX6UL_CLK_CKO2_PODF 229
|
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#define IMX6UL_CLK_CKO2 230
|
||||
#define IMX6UL_CLK_CKO 231
|
||||
|
||||
/* For i.MX6ULL */
|
||||
#define IMX6ULL_CLK_ESAI_PRED 225
|
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#define IMX6ULL_CLK_ESAI_PODF 226
|
||||
#define IMX6ULL_CLK_ESAI_EXTAL 227
|
||||
#define IMX6ULL_CLK_ESAI_MEM 228
|
||||
#define IMX6ULL_CLK_ESAI_IPG 229
|
||||
#define IMX6ULL_CLK_DCP_CLK 230
|
||||
#define IMX6ULL_CLK_EPDC_PRE_SEL 231
|
||||
#define IMX6ULL_CLK_EPDC_SEL 232
|
||||
#define IMX6ULL_CLK_EPDC_PODF 233
|
||||
#define IMX6ULL_CLK_EPDC_ACLK 234
|
||||
#define IMX6ULL_CLK_EPDC_PIX 235
|
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#define IMX6ULL_CLK_ESAI_SEL 236
|
||||
#define IMX6UL_CLK_END 237
|
||||
#define IMX6ULL_CLK_ESAI_PRED 232
|
||||
#define IMX6ULL_CLK_ESAI_PODF 233
|
||||
#define IMX6ULL_CLK_ESAI_EXTAL 234
|
||||
#define IMX6ULL_CLK_ESAI_MEM 235
|
||||
#define IMX6ULL_CLK_ESAI_IPG 236
|
||||
#define IMX6ULL_CLK_DCP_CLK 237
|
||||
#define IMX6ULL_CLK_EPDC_PRE_SEL 238
|
||||
#define IMX6ULL_CLK_EPDC_SEL 239
|
||||
#define IMX6ULL_CLK_EPDC_PODF 240
|
||||
#define IMX6ULL_CLK_EPDC_ACLK 241
|
||||
#define IMX6ULL_CLK_EPDC_PIX 242
|
||||
#define IMX6ULL_CLK_ESAI_SEL 243
|
||||
#define IMX6UL_CLK_END 244
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
|
||||
|
|
|
|||
|
|
@ -171,13 +171,12 @@
|
|||
#define CLK_TOP_8BDAC 151
|
||||
#define CLK_TOP_WBG_DIG_416M 152
|
||||
#define CLK_TOP_DPI 153
|
||||
#define CLK_TOP_HDMITX_CLKDIG_CTS 154
|
||||
#define CLK_TOP_DSI0_LNTC_DSI 155
|
||||
#define CLK_TOP_AUD_EXT1 156
|
||||
#define CLK_TOP_AUD_EXT2 157
|
||||
#define CLK_TOP_NFI1X_PAD 158
|
||||
#define CLK_TOP_AXISEL_D4 159
|
||||
#define CLK_TOP_NR 160
|
||||
#define CLK_TOP_DSI0_LNTC_DSI 154
|
||||
#define CLK_TOP_AUD_EXT1 155
|
||||
#define CLK_TOP_AUD_EXT2 156
|
||||
#define CLK_TOP_NFI1X_PAD 157
|
||||
#define CLK_TOP_AXISEL_D4 158
|
||||
#define CLK_TOP_NR 159
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
|
|
@ -194,7 +193,8 @@
|
|||
#define CLK_APMIXED_HADDS2PLL 11
|
||||
#define CLK_APMIXED_AUD2PLL 12
|
||||
#define CLK_APMIXED_TVD2PLL 13
|
||||
#define CLK_APMIXED_NR 14
|
||||
#define CLK_APMIXED_HDMI_REF 14
|
||||
#define CLK_APMIXED_NR 15
|
||||
|
||||
/* DDRPHY */
|
||||
|
||||
|
|
@ -431,6 +431,10 @@
|
|||
#define CLK_ETHSYS_CRYPTO 8
|
||||
#define CLK_ETHSYS_NR 9
|
||||
|
||||
/* G3DSYS */
|
||||
#define CLK_G3DSYS_CORE 1
|
||||
#define CLK_G3DSYS_NR 2
|
||||
|
||||
/* BDP */
|
||||
|
||||
#define CLK_BDP_BRG_BA 1
|
||||
|
|
|
|||
|
|
@ -87,4 +87,7 @@
|
|||
#define MT2701_ETHSYS_GMAC_RST 23
|
||||
#define MT2701_ETHSYS_PPE_RST 31
|
||||
|
||||
/* G3DSYS resets */
|
||||
#define MT2701_G3DSYS_CORE_RST 0
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue