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Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: 6994/1: smp_twd: Fix typo in 'twd_timer_rate' printing
  ARM: 6987/1: l2x0: fix disabling function to avoid deadlock
  ARM: 6966/1: ep93xx: fix inverted RTS/DTR signals on uart1
  ARM: 6980/1: mmci: use StartBitErr to detect bad connections
  ARM: 6979/1: mach-vt8500: add forgotten irq_data conversion
  ARM: move memory layout sanity checking before meminfo initialization
  ARM: 6990/1: MAINTAINERS: add entry for ARM PMU profiling and debugging
  ARM: 6989/1: perf: do not start the PMU when no events are present
  ARM: dmabounce: fix map_single() error return value
This commit is contained in:
Linus Torvalds 2011-07-10 07:28:30 -07:00
parent 8733449b7c 90c5ffe592
commit 7fc7693627
12 changed files with 58 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
MAINTAINERS
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@ -594,6 +594,16 @@ S: Maintained
F: arch/arm/lib/floppydma.S F: arch/arm/lib/floppydma.S
F: arch/arm/include/asm/floppy.h F: arch/arm/include/asm/floppy.h
ARM PMU PROFILING AND DEBUGGING
M: Will Deacon <will.deacon@arm.com>
S: Maintained
F: arch/arm/kernel/perf_event*
F: arch/arm/oprofile/common.c
F: arch/arm/kernel/pmu.c
F: arch/arm/include/asm/pmu.h
F: arch/arm/kernel/hw_breakpoint.c
F: arch/arm/include/asm/hw_breakpoint.h
ARM PORT ARM PORT
M: Russell King <linux@arm.linux.org.uk> M: Russell King <linux@arm.linux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

2
arch/arm/common/dmabounce.c
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@ -255,7 +255,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
if (buf == 0) { if (buf == 0) {
dev_err(dev, "%s: unable to map unsafe buffer %p!\n", dev_err(dev, "%s: unable to map unsafe buffer %p!\n",
__func__, ptr); __func__, ptr);
return 0; return ~0;
} }
dev_dbg(dev, dev_dbg(dev,

6
arch/arm/kernel/perf_event.c
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@ -583,7 +583,7 @@ static int armpmu_event_init(struct perf_event *event)
static void armpmu_enable(struct pmu *pmu) static void armpmu_enable(struct pmu *pmu)
{ {
/* Enable all of the perf events on hardware. */ /* Enable all of the perf events on hardware. */
int idx; int idx, enabled = 0;
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
if (!armpmu) if (!armpmu)
@ -596,9 +596,11 @@ static void armpmu_enable(struct pmu *pmu)
continue; continue;
armpmu->enable(&event->hw, idx); armpmu->enable(&event->hw, idx);
enabled = 1;
} }
armpmu->start(); if (enabled)
armpmu->start();
} }
static void armpmu_disable(struct pmu *pmu) static void armpmu_disable(struct pmu *pmu)

2
arch/arm/kernel/setup.c
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@ -73,6 +73,7 @@ __setup("fpe=", fpe_setup);
#endif #endif
extern void paging_init(struct machine_desc *desc); extern void paging_init(struct machine_desc *desc);
extern void sanity_check_meminfo(void);
extern void reboot_setup(char *str); extern void reboot_setup(char *str);
unsigned int processor_id; unsigned int processor_id;
@ -900,6 +901,7 @@ void __init setup_arch(char **cmdline_p)
parse_early_param(); parse_early_param();
sanity_check_meminfo();
arm_memblock_init(&meminfo, mdesc); arm_memblock_init(&meminfo, mdesc);
paging_init(mdesc); paging_init(mdesc);

2
arch/arm/kernel/smp_twd.c
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@ -115,7 +115,7 @@ static void __cpuinit twd_calibrate_rate(void)
twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000, printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
(twd_timer_rate / 1000000) % 100); (twd_timer_rate / 10000) % 100);
} }
} }

4
arch/arm/mach-ep93xx/core.c
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@ -251,9 +251,9 @@ static void ep93xx_uart_set_mctrl(struct amba_device *dev,
unsigned int mcr; unsigned int mcr;
mcr = 0; mcr = 0;
if (!(mctrl & TIOCM_RTS)) if (mctrl & TIOCM_RTS)
mcr |= 2; mcr |= 2;
if (!(mctrl & TIOCM_DTR)) if (mctrl & TIOCM_DTR)
mcr |= 1; mcr |= 1;
__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);

21
arch/arm/mach-vt8500/irq.c
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@ -39,9 +39,10 @@
static void __iomem *ic_regbase; static void __iomem *ic_regbase;
static void __iomem *sic_regbase; static void __iomem *sic_regbase;
static void vt8500_irq_mask(unsigned int irq) static void vt8500_irq_mask(struct irq_data *d)
{ {
void __iomem *base = ic_regbase; void __iomem *base = ic_regbase;
unsigned irq = d->irq;
u8 edge; u8 edge;
if (irq >= 64) { if (irq >= 64) {
@ -64,9 +65,10 @@ static void vt8500_irq_mask(unsigned int irq)
} }
} }
static void vt8500_irq_unmask(unsigned int irq) static void vt8500_irq_unmask(struct irq_data *d)
{ {
void __iomem *base = ic_regbase; void __iomem *base = ic_regbase;
unsigned irq = d->irq;
u8 dctr; u8 dctr;
if (irq >= 64) { if (irq >= 64) {
@ -78,10 +80,11 @@ static void vt8500_irq_unmask(unsigned int irq)
writeb(dctr, base + VT8500_IC_DCTR + irq); writeb(dctr, base + VT8500_IC_DCTR + irq);
} }
static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
{ {
void __iomem *base = ic_regbase; void __iomem *base = ic_regbase;
unsigned int orig_irq = irq; unsigned irq = d->irq;
unsigned orig_irq = irq;
u8 dctr; u8 dctr;
if (irq >= 64) { if (irq >= 64) {
@ -114,11 +117,11 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
} }
static struct irq_chip vt8500_irq_chip = { static struct irq_chip vt8500_irq_chip = {
.name = "vt8500", .name = "vt8500",
.ack = vt8500_irq_mask, .irq_ack = vt8500_irq_mask,
.mask = vt8500_irq_mask, .irq_mask = vt8500_irq_mask,
.unmask = vt8500_irq_unmask, .irq_unmask = vt8500_irq_unmask,
.set_type = vt8500_irq_set_type, .irq_set_type = vt8500_irq_set_type,
}; };
void __init vt8500_init_irq(void) void __init vt8500_init_irq(void)

19
arch/arm/mm/cache-l2x0.c
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@ -120,17 +120,22 @@ static void l2x0_cache_sync(void)
spin_unlock_irqrestore(&l2x0_lock, flags); spin_unlock_irqrestore(&l2x0_lock, flags);
} }
static void __l2x0_flush_all(void)
{
debug_writel(0x03);
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
cache_sync();
debug_writel(0x00);
}
static void l2x0_flush_all(void) static void l2x0_flush_all(void)
{ {
unsigned long flags; unsigned long flags;
/* clean all ways */ /* clean all ways */
spin_lock_irqsave(&l2x0_lock, flags); spin_lock_irqsave(&l2x0_lock, flags);
debug_writel(0x03); __l2x0_flush_all();
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
cache_sync();
debug_writel(0x00);
spin_unlock_irqrestore(&l2x0_lock, flags); spin_unlock_irqrestore(&l2x0_lock, flags);
} }
@ -266,7 +271,9 @@ static void l2x0_disable(void)
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&l2x0_lock, flags); spin_lock_irqsave(&l2x0_lock, flags);
writel(0, l2x0_base + L2X0_CTRL); __l2x0_flush_all();
writel_relaxed(0, l2x0_base + L2X0_CTRL);
dsb();
spin_unlock_irqrestore(&l2x0_lock, flags); spin_unlock_irqrestore(&l2x0_lock, flags);
} }

5
arch/arm/mm/mmu.c
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@ -759,7 +759,7 @@ early_param("vmalloc", early_vmalloc);
static phys_addr_t lowmem_limit __initdata = 0; static phys_addr_t lowmem_limit __initdata = 0;
static void __init sanity_check_meminfo(void) void __init sanity_check_meminfo(void)
{ {
int i, j, highmem = 0; int i, j, highmem = 0;
@ -1032,8 +1032,9 @@ void __init paging_init(struct machine_desc *mdesc)
{ {
void *zero_page; void *zero_page;
memblock_set_current_limit(lowmem_limit);
build_mem_type_table(); build_mem_type_table();
sanity_check_meminfo();
prepare_page_table(); prepare_page_table();
map_lowmem(); map_lowmem();
devicemaps_init(mdesc); devicemaps_init(mdesc);

4
arch/arm/mm/nommu.c
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@ -27,6 +27,10 @@ void __init arm_mm_memblock_reserve(void)
memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE); memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
} }
void __init sanity_check_meminfo(void)
{
}
/* /*
* paging_init() sets up the page tables, initialises the zone memory * paging_init() sets up the page tables, initialises the zone memory
* maps, and sets up the zero page, bad page and bad page tables. * maps, and sets up the zero page, bad page and bad page tables.

2
drivers/mmc/host/mmci.c
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@ -582,6 +582,8 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
data->error = -EILSEQ; data->error = -EILSEQ;
} else if (status & MCI_DATATIMEOUT) { } else if (status & MCI_DATATIMEOUT) {
data->error = -ETIMEDOUT; data->error = -ETIMEDOUT;
} else if (status & MCI_STARTBITERR) {
data->error = -ECOMM;
} else if (status & MCI_TXUNDERRUN) { } else if (status & MCI_TXUNDERRUN) {
data->error = -EIO; data->error = -EIO;
} else if (status & MCI_RXOVERRUN) { } else if (status & MCI_RXOVERRUN) {

5
drivers/mmc/host/mmci.h
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@ -86,6 +86,7 @@
#define MCI_CMDRESPEND (1 << 6) #define MCI_CMDRESPEND (1 << 6)
#define MCI_CMDSENT (1 << 7) #define MCI_CMDSENT (1 << 7)
#define MCI_DATAEND (1 << 8) #define MCI_DATAEND (1 << 8)
#define MCI_STARTBITERR (1 << 9)
#define MCI_DATABLOCKEND (1 << 10) #define MCI_DATABLOCKEND (1 << 10)
#define MCI_CMDACTIVE (1 << 11) #define MCI_CMDACTIVE (1 << 11)
#define MCI_TXACTIVE (1 << 12) #define MCI_TXACTIVE (1 << 12)
@ -112,6 +113,7 @@
#define MCI_CMDRESPENDCLR (1 << 6) #define MCI_CMDRESPENDCLR (1 << 6)
#define MCI_CMDSENTCLR (1 << 7) #define MCI_CMDSENTCLR (1 << 7)
#define MCI_DATAENDCLR (1 << 8) #define MCI_DATAENDCLR (1 << 8)
#define MCI_STARTBITERRCLR (1 << 9)
#define MCI_DATABLOCKENDCLR (1 << 10) #define MCI_DATABLOCKENDCLR (1 << 10)
/* Extended status bits for the ST Micro variants */ /* Extended status bits for the ST Micro variants */
#define MCI_ST_SDIOITC (1 << 22) #define MCI_ST_SDIOITC (1 << 22)
@ -127,6 +129,7 @@
#define MCI_CMDRESPENDMASK (1 << 6) #define MCI_CMDRESPENDMASK (1 << 6)
#define MCI_CMDSENTMASK (1 << 7) #define MCI_CMDSENTMASK (1 << 7)
#define MCI_DATAENDMASK (1 << 8) #define MCI_DATAENDMASK (1 << 8)
#define MCI_STARTBITERRMASK (1 << 9)
#define MCI_DATABLOCKENDMASK (1 << 10) #define MCI_DATABLOCKENDMASK (1 << 10)
#define MCI_CMDACTIVEMASK (1 << 11) #define MCI_CMDACTIVEMASK (1 << 11)
#define MCI_TXACTIVEMASK (1 << 12) #define MCI_TXACTIVEMASK (1 << 12)
@ -150,7 +153,7 @@
#define MCI_IRQENABLE \ #define MCI_IRQENABLE \
(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
MCI_CMDRESPENDMASK|MCI_CMDSENTMASK) MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)
/* These interrupts are directed to IRQ1 when two IRQ lines are available */ /* These interrupts are directed to IRQ1 when two IRQ lines are available */
#define MCI_IRQ1MASK \ #define MCI_IRQ1MASK \