mirror of https://gitee.com/openkylin/linux.git
drm/radeon: RS600: fix interrupt handling
the checks weren't updated when RS600 support was added. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
parent
a7d13ad0e2
commit
800b699511
|
@ -46,7 +46,7 @@ static int radeon_suspend(struct drm_device *dev, pm_message_t state)
|
|||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
/* Disable *all* interrupts */
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
|
||||
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
|
||||
return 0;
|
||||
|
@ -57,7 +57,7 @@ static int radeon_resume(struct drm_device *dev)
|
|||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
/* Restore interrupt registers */
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
|
||||
RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
|
||||
return 0;
|
||||
|
|
|
@ -65,7 +65,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
|
|||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
|
||||
switch (crtc) {
|
||||
case 0:
|
||||
r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
|
||||
|
@ -100,7 +100,7 @@ void radeon_disable_vblank(struct drm_device *dev, int crtc)
|
|||
{
|
||||
drm_radeon_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
|
||||
switch (crtc) {
|
||||
case 0:
|
||||
r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
|
||||
|
@ -135,7 +135,7 @@ static inline u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r
|
|||
u32 irq_mask = RADEON_SW_INT_TEST;
|
||||
|
||||
*r500_disp_int = 0;
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
|
||||
/* vbl interrupts in a different place */
|
||||
|
||||
if (irqs & R500_DISPLAY_INT_STATUS) {
|
||||
|
@ -202,7 +202,7 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
|
|||
DRM_WAKEUP(&dev_priv->swi_queue);
|
||||
|
||||
/* VBLANK interrupt */
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
|
||||
if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
|
||||
drm_handle_vblank(dev, 0);
|
||||
if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
|
||||
|
@ -265,7 +265,7 @@ u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
|
||||
if (crtc == 0)
|
||||
return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
|
||||
else
|
||||
|
@ -327,7 +327,7 @@ void radeon_driver_irq_preinstall(struct drm_device * dev)
|
|||
u32 dummy;
|
||||
|
||||
/* Disable *all* interrupts */
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
|
||||
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
|
||||
|
||||
|
@ -357,7 +357,7 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
|
|||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
|
||||
RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
|
||||
/* Disable *all* interrupts */
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
|
||||
|
|
Loading…
Reference in New Issue