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MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA 

The config0 register in the Xburst CPUs with a processor ID of
PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
but they don't actually support this ISA.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Paul Cercueil 2019-05-08 00:17:55 +02:00 committed by Paul Burton
parent 1b1f01b653
commit 8041edb592
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1 changed files with 8 additions and 0 deletions
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8
arch/mips/kernel/cpu-probe.c
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@ -1973,6 +1973,14 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
panic("Unknown Ingenic Processor ID!"); panic("Unknown Ingenic Processor ID!");
break; break;
} }
/*
* The config0 register in the Xburst CPUs with a processor ID of
* PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
* but they don't actually support this ISA.
*/
if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
c->isa_level &= ~MIPS_CPU_ISA_M32R2;
} }
static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)