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powerpc: Use a function for getting the instruction op code 

In preparation for using a data type for instructions that can not be
directly used with the '>>' operator use a function for getting the op
code of an instruction.

Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
Reviewed-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200506034050.24806-9-jniethe5@gmail.com
This commit is contained in:
Jordan Niethe 2020-05-06 13:40:28 +10:00 committed by Michael Ellerman
parent 777e26f0ed
commit 8094892d1a
6 changed files with 13 additions and 6 deletions
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5
arch/powerpc/include/asm/inst.h
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@ -13,4 +13,9 @@ static inline u32 ppc_inst_val(u32 x)
return x; return x;
} }
static inline int ppc_inst_primary_opcode(u32 x)
{
return ppc_inst_val(x) >> 26;
}
#endif /* _ASM_POWERPC_INST_H */ #endif /* _ASM_POWERPC_INST_H */

2
arch/powerpc/kernel/align.c
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@ -314,7 +314,7 @@ int fix_alignment(struct pt_regs *regs)
} }
#ifdef CONFIG_SPE #ifdef CONFIG_SPE
if ((ppc_inst_val(instr) >> 26) == 0x4) { if (ppc_inst_primary_opcode(instr) == 0x4) {
int reg = (ppc_inst_val(instr) >> 21) & 0x1f; int reg = (ppc_inst_val(instr) >> 21) & 0x1f;
PPC_WARN_ALIGNMENT(spe, regs); PPC_WARN_ALIGNMENT(spe, regs);
return emulate_spe(regs, reg, instr); return emulate_spe(regs, reg, instr);

3
arch/powerpc/kernel/vecemu.c
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@ -10,6 +10,7 @@
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/switch_to.h> #include <asm/switch_to.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <asm/inst.h>
/* Functions in vector.S */ /* Functions in vector.S */
extern void vaddfp(vector128 *dst, vector128 *a, vector128 *b); extern void vaddfp(vector128 *dst, vector128 *a, vector128 *b);
@ -268,7 +269,7 @@ int emulate_altivec(struct pt_regs *regs)
return -EFAULT; return -EFAULT;
word = ppc_inst_val(instr); word = ppc_inst_val(instr);
if ((word >> 26) != 4) if (ppc_inst_primary_opcode(instr) != 4)
return -EINVAL; /* not an altivec instruction */ return -EINVAL; /* not an altivec instruction */
vd = (word >> 21) & 0x1f; vd = (word >> 21) & 0x1f;
va = (word >> 16) & 0x1f; va = (word >> 16) & 0x1f;

4
arch/powerpc/lib/code-patching.c
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@ -231,7 +231,7 @@ bool is_offset_in_branch_range(long offset)
*/ */
bool is_conditional_branch(unsigned int instr) bool is_conditional_branch(unsigned int instr)
{ {
unsigned int opcode = instr >> 26; unsigned int opcode = ppc_inst_primary_opcode(instr);
if (opcode == 16) /* bc, bca, bcl, bcla */ if (opcode == 16) /* bc, bca, bcl, bcla */
return true; return true;
@ -289,7 +289,7 @@ int create_cond_branch(unsigned int *instr, const unsigned int *addr,
static unsigned int branch_opcode(unsigned int instr) static unsigned int branch_opcode(unsigned int instr)
{ {
return (instr >> 26) & 0x3F; return ppc_inst_primary_opcode(instr) & 0x3F;
} }
static int instr_is_branch_iform(unsigned int instr) static int instr_is_branch_iform(unsigned int instr)

2
arch/powerpc/lib/sstep.c
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@ -1175,7 +1175,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
word = ppc_inst_val(instr); word = ppc_inst_val(instr);
op->type = COMPUTE; op->type = COMPUTE;
opcode = instr >> 26; opcode = ppc_inst_primary_opcode(instr);
switch (opcode) { switch (opcode) {
case 16: /* bc */ case 16: /* bc */
op->type = BRANCH; op->type = BRANCH;

3
arch/powerpc/mm/fault.c
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@ -41,6 +41,7 @@
#include <asm/siginfo.h> #include <asm/siginfo.h>
#include <asm/debug.h> #include <asm/debug.h>
#include <asm/kup.h> #include <asm/kup.h>
#include <asm/inst.h>
/* /*
* Check whether the instruction inst is a store using * Check whether the instruction inst is a store using
@ -52,7 +53,7 @@ static bool store_updates_sp(unsigned int inst)
if (((ppc_inst_val(inst) >> 16) & 0x1f) != 1) if (((ppc_inst_val(inst) >> 16) & 0x1f) != 1)
return false; return false;
/* check major opcode */ /* check major opcode */
switch (inst >> 26) { switch (ppc_inst_primary_opcode(inst)) {
case OP_STWU: case OP_STWU:
case OP_STBU: case OP_STBU:
case OP_STHU: case OP_STHU: