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ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN 

Framebuffer driver needs to fetch the video data during the rising
edge of the VCLK. Otherwise, there are some glitches in the LCD
display.

Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tushar Behera 2011-12-29 16:48:08 +09:00 committed by Kukjin Kim
parent 6e11e0bd82
commit 815ed6fc0a
1 changed files with 2 additions and 1 deletions
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3
arch/arm/mach-exynos/mach-origen.c
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@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = {
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
.win[0] = &origen_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
VIDCON1_INV_VCLK,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};