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OpenRISC: IRQ
This patch adds support for the OpenRISC PIC. Signed-off-by: Jonas Bonn <jonas@southpole.se> Cc: tglx@linutronix.de Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Jonas Bonn
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* et al.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __ASM_OPENRISC_IRQ_H__
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#define __ASM_OPENRISC_IRQ_H__
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#define NR_IRQS 32
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#include <asm-generic/irq.h>
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#define NO_IRQ (-1)
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#endif /* __ASM_OPENRISC_IRQ_H__ */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* et al.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef ___ASM_OPENRISC_IRQFLAGS_H
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#define ___ASM_OPENRISC_IRQFLAGS_H
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#include <asm/spr_defs.h>
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#define ARCH_IRQ_DISABLED 0x00
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#define ARCH_IRQ_ENABLED (SPR_SR_IEE|SPR_SR_TEE)
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#include <asm-generic/irqflags.h>
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#endif /* ___ASM_OPENRISC_IRQFLAGS_H */
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/*
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* OpenRISC irq.c
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* Modifications for the OpenRISC architecture:
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/ftrace.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/kernel_stat.h>
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#include <linux/irqflags.h>
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/* read interrupt enabled status */
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unsigned long arch_local_save_flags(void)
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{
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return mfspr(SPR_SR) & (SPR_SR_IEE|SPR_SR_TEE);
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}
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EXPORT_SYMBOL(arch_local_save_flags);
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/* set interrupt enabled status */
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void arch_local_irq_restore(unsigned long flags)
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{
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mtspr(SPR_SR, ((mfspr(SPR_SR) & ~(SPR_SR_IEE|SPR_SR_TEE)) | flags));
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}
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EXPORT_SYMBOL(arch_local_irq_restore);
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/* OR1K PIC implementation */
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/* We're a couple of cycles faster than the generic implementations with
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* these 'fast' versions.
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*/
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static void or1k_pic_mask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->irq));
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}
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static void or1k_pic_unmask(struct irq_data *data)
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{
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mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->irq));
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}
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static void or1k_pic_ack(struct irq_data *data)
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{
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/* EDGE-triggered interrupts need to be ack'ed in order to clear
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* the latch.
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* LEVER-triggered interrupts do not need to be ack'ed; however,
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* ack'ing the interrupt has no ill-effect and is quicker than
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* trying to figure out what type it is...
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*/
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/* The OpenRISC 1000 spec says to write a 1 to the bit to ack the
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* interrupt, but the OR1200 does this backwards and requires a 0
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* to be written...
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*/
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#ifdef CONFIG_OR1K_1200
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/* There are two oddities with the OR1200 PIC implementation:
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* i) LEVEL-triggered interrupts are latched and need to be cleared
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* ii) the interrupt latch is cleared by writing a 0 to the bit,
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* as opposed to a 1 as mandated by the spec
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*/
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq));
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#else
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WARN(1, "Interrupt handling possibily broken\n");
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mtspr(SPR_PICSR, (1UL << irq));
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#endif
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}
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static void or1k_pic_mask_ack(struct irq_data *data)
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{
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/* Comments for pic_ack apply here, too */
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#ifdef CONFIG_OR1K_1200
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mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq));
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#else
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WARN(1, "Interrupt handling possibily broken\n");
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mtspr(SPR_PICSR, (1UL << irq));
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#endif
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}
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static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)
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{
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/* There's nothing to do in the PIC configuration when changing
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* flow type. Level and edge-triggered interrupts are both
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* supported, but it's PIC-implementation specific which type
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* is handled. */
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return irq_setup_alt_chip(data, flow_type);
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}
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static inline int pic_get_irq(int first)
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{
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int irq;
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irq = ffs(mfspr(SPR_PICSR) >> first);
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return irq ? irq + first - 1 : NO_IRQ;
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}
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static void __init or1k_irq_init(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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/* Disable all interrupts until explicitly requested */
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mtspr(SPR_PICMR, (0UL));
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gc = irq_alloc_generic_chip("or1k-PIC", 1, 0, 0, handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_unmask = or1k_pic_unmask;
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ct->chip.irq_mask = or1k_pic_mask;
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ct->chip.irq_ack = or1k_pic_ack;
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ct->chip.irq_mask_ack = or1k_pic_mask_ack;
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ct->chip.irq_set_type = or1k_pic_set_type;
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/* The OR1K PIC can handle both level and edge trigged
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* interrupts in roughly the same manner
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*/
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#if 0
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/* FIXME: chip.type??? */
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ct->chip.type = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK;
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#endif
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irq_setup_generic_chip(gc, IRQ_MSK(NR_IRQS), 0,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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}
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void __init init_IRQ(void)
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{
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or1k_irq_init();
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}
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void __irq_entry do_IRQ(struct pt_regs *regs)
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{
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int irq = -1;
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struct pt_regs *old_regs = set_irq_regs(regs);
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irq_enter();
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while ((irq = pic_get_irq(irq + 1)) != NO_IRQ)
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generic_handle_irq(irq);
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irq_exit();
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set_irq_regs(old_regs);
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}
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unsigned int irq_create_of_mapping(struct device_node *controller,
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const u32 *intspec, unsigned int intsize)
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{
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return intspec[0];
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}
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EXPORT_SYMBOL_GPL(irq_create_of_mapping);
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