mirror of https://gitee.com/openkylin/linux.git
OMAP2PLUS: DSS2: FEATURES: Function to Provide the max fck supported
The maximum supported frequency for DSS has increased from 173 to 186 Mhz on OMAP4. Introduce a dss feature function to get the max_fck to replace DISPC_MAX_FCK macro. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -38,6 +38,7 @@
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#include <plat/clock.h>
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#include "dss.h"
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#include "dss_features.h"
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/*#define VERBOSE_IRQ*/
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#define DSI_CATCH_MISSING_TE
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@ -856,10 +857,12 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
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struct dispc_clock_info best_dispc;
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int min_fck_per_pck;
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int match = 0;
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unsigned long dss_clk_fck2;
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unsigned long dss_clk_fck2, max_dss_fck;
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dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
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max_dss_fck = dss_feat_get_max_dss_fck();
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if (req_pck == dsi.cache_req_pck &&
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dsi.cache_cinfo.clkin == dss_clk_fck2) {
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DSSDBG("DSI clock info found from cache\n");
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@ -872,7 +875,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
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req_pck * min_fck_per_pck > max_dss_fck) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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@ -925,7 +928,7 @@ int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
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if (cur.dsi1_pll_fclk < req_pck)
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break;
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if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
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if (cur.dsi1_pll_fclk > max_dss_fck)
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continue;
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if (min_fck_per_pck &&
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@ -387,7 +387,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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struct dss_clock_info best_dss;
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struct dispc_clock_info best_dispc;
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unsigned long fck;
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unsigned long fck, max_dss_fck;
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u16 fck_div;
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@ -396,6 +396,8 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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prate = dss_get_dpll4_rate();
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max_dss_fck = dss_feat_get_max_dss_fck();
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fck = dss_clk_get_rate(DSS_CLK_FCK);
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if (req_pck == dss.cache_req_pck &&
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((cpu_is_omap34xx() && prate == dss.cache_prate) ||
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@ -409,7 +411,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
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if (min_fck_per_pck &&
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req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
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req_pck * min_fck_per_pck > max_dss_fck) {
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DSSERR("Requested pixel clock not possible with the current "
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"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
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"the constraint off.\n");
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@ -445,7 +447,7 @@ int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
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else
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fck = prate / fck_div * 2;
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if (fck > DISPC_MAX_FCK)
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if (fck > max_dss_fck)
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continue;
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if (min_fck_per_pck &&
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@ -97,8 +97,6 @@ extern unsigned int dss_debug;
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#define FLD_MOD(orig, val, start, end) \
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(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
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#define DISPC_MAX_FCK 173000000
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enum omap_burst_size {
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OMAP_DSS_BURST_4x32 = 0,
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OMAP_DSS_BURST_8x32 = 1,
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@ -41,6 +41,7 @@ struct omap_dss_features {
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const int num_mgrs;
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const int num_ovls;
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const unsigned long max_dss_fck;
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const enum omap_display_type *supported_displays;
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const enum omap_color_mode *supported_color_modes;
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};
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@ -168,6 +169,7 @@ static struct omap_dss_features omap2_dss_features = {
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.num_mgrs = 2,
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.num_ovls = 3,
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.max_dss_fck = 173000000,
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.supported_displays = omap2_dss_supported_displays,
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.supported_color_modes = omap2_dss_supported_color_modes,
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};
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@ -185,6 +187,7 @@ static struct omap_dss_features omap3430_dss_features = {
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.num_mgrs = 2,
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.num_ovls = 3,
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.max_dss_fck = 173000000,
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.supported_displays = omap3430_dss_supported_displays,
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.supported_color_modes = omap3_dss_supported_color_modes,
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};
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@ -202,6 +205,7 @@ static struct omap_dss_features omap3630_dss_features = {
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.num_mgrs = 2,
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.num_ovls = 3,
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.max_dss_fck = 173000000,
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.supported_displays = omap3630_dss_supported_displays,
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.supported_color_modes = omap3_dss_supported_color_modes,
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};
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@ -217,6 +221,7 @@ static struct omap_dss_features omap4_dss_features = {
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.num_mgrs = 3,
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.num_ovls = 3,
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.max_dss_fck = 186000000,
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.supported_displays = omap4_dss_supported_displays,
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.supported_color_modes = omap3_dss_supported_color_modes,
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};
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@ -232,6 +237,12 @@ int dss_feat_get_num_ovls(void)
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return omap_current_dss_features->num_ovls;
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}
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/* Max supported DSS FCK in Hz */
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unsigned long dss_feat_get_max_dss_fck(void)
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{
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return omap_current_dss_features->max_dss_fck;
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}
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enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
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{
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return omap_current_dss_features->supported_displays[channel];
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@ -52,6 +52,7 @@ enum dss_feat_reg_field {
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/* DSS Feature Functions */
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int dss_feat_get_num_mgrs(void);
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int dss_feat_get_num_ovls(void);
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unsigned long dss_feat_get_max_dss_fck(void);
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enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
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enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
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bool dss_feat_color_mode_supported(enum omap_plane plane,
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