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KVM: x86 emulator: decode extended accumulator explicity 

Single-operand MUL and DIV access an extended accumulator: AX for byte
instructions, and DX:AX, EDX:EAX, or RDX:RAX for larger-sized instructions.
Add support for fetching the extended accumulator.

In order not to change things too much, RDX is loaded into Src2, which is
already loaded by fastop().  This avoids increasing register pressure on
i386.

Gleb: disable src writeback for ByteOp div/mul.

Signed-off-by: Avi Kivity <avi.kivity@gmail.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
This commit is contained in:
Avi Kivity 2013-02-09 11:31:45 +02:00 committed by Gleb Natapov
parent fb32b1eda2
commit 820207c8fc
1 changed files with 24 additions and 0 deletions
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24
arch/x86/kvm/emulate.c
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@ -61,6 +61,8 @@
#define OpMem8 26ull /* 8-bit zero extended memory operand */ #define OpMem8 26ull /* 8-bit zero extended memory operand */
#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
#define OpBits 5 /* Width of operand field */ #define OpBits 5 /* Width of operand field */
#define OpMask ((1ull << OpBits) - 1) #define OpMask ((1ull << OpBits) - 1)
@ -86,6 +88,7 @@
#define DstMem64 (OpMem64 << DstShift) #define DstMem64 (OpMem64 << DstShift)
#define DstImmUByte (OpImmUByte << DstShift) #define DstImmUByte (OpImmUByte << DstShift)
#define DstDX (OpDX << DstShift) #define DstDX (OpDX << DstShift)
#define DstAccLo (OpAccLo << DstShift)
#define DstMask (OpMask << DstShift) #define DstMask (OpMask << DstShift)
/* Source operand type. */ /* Source operand type. */
#define SrcShift 6 #define SrcShift 6
@ -108,6 +111,7 @@
#define SrcImm64 (OpImm64 << SrcShift) #define SrcImm64 (OpImm64 << SrcShift)
#define SrcDX (OpDX << SrcShift) #define SrcDX (OpDX << SrcShift)
#define SrcMem8 (OpMem8 << SrcShift) #define SrcMem8 (OpMem8 << SrcShift)
#define SrcAccHi (OpAccHi << SrcShift)
#define SrcMask (OpMask << SrcShift) #define SrcMask (OpMask << SrcShift)
#define BitOp (1<<11) #define BitOp (1<<11)
#define MemAbs (1<<12) /* Memory operand is absolute displacement */ #define MemAbs (1<<12) /* Memory operand is absolute displacement */
@ -157,6 +161,8 @@
#define NoWrite ((u64)1 << 45) /* No writeback */ #define NoWrite ((u64)1 << 45) /* No writeback */
#define SrcWrite ((u64)1 << 46) /* Write back src operand */ #define SrcWrite ((u64)1 << 46) /* Write back src operand */
#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
#define X2(x...) x, x #define X2(x...) x, x
#define X3(x...) X2(x), x #define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x) #define X4(x...) X2(x), X2(x)
@ -4166,6 +4172,24 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
fetch_register_operand(op); fetch_register_operand(op);
op->orig_val = op->val; op->orig_val = op->val;
break; break;
case OpAccLo:
op->type = OP_REG;
op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
fetch_register_operand(op);
op->orig_val = op->val;
break;
case OpAccHi:
if (ctxt->d & ByteOp) {
op->type = OP_NONE;
break;
}
op->type = OP_REG;
op->bytes = ctxt->op_bytes;
op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
fetch_register_operand(op);
op->orig_val = op->val;
break;
case OpDI: case OpDI:
op->type = OP_MEM; op->type = OP_MEM;
op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;