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All iommus got their clocks added and rk3399 got support for its 

usb3-phy otg-port and better ajustment for the cpll child clocks.
 On the board side, all rk3399 got their typec phys enabled - which
 is needed for better usb support, the sapphire board got some more
 properties moved to the excavator baseboard where they really belong,
 kevin got a fix to use a real devicetree compatible and puma-haikou
 got its hdmi port enabled.
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Merge tag 'v4.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

All iommus got their clocks added and rk3399 got support for its
usb3-phy otg-port and better ajustment for the cpll child clocks.
On the board side, all rk3399 got their typec phys enabled - which
is needed for better usb support, the sapphire board got some more
properties moved to the excavator baseboard where they really belong,
kevin got a fix to use a real devicetree compatible and puma-haikou
got its hdmi port enabled.

* tag 'v4.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: enable hdmi on rk3399-puma-haikou
  arm64: dts: rockchip: use canonical compatible for touchpad/touchscreen on gru-kevin
  arm64: dts: rockchip: add clocks in iommu nodes
  arm64: dts: rockchip: add usb3-phy otg-port support for rk3399
  arm64: dts: rockchip: remove PCIe assigned-clocks in excavator baseboard
  arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard
  arm64: dts: rockchip: assign clock rate for cpll child clocks on rk3399
  arm64: dts: rockchip: enable typec-phy0 for rk3399-puma-haikou
  arm64: dts: rockchip: enable typec-phy1 for rk3399-puma
  arm64: dts: rockchip: enable typec-phy for rk3399-firefly
  arm64: dts: rockchip: enable typec-phy for rk3399-sapphire

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-05-15 13:52:13 -07:00
parent 80dedbe0a8 17bd073794
commit 823927bdb9
10 changed files with 111 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -595,6 +595,8 @@ h265e_mmu: iommu@ff330200 {
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265e_mmu";
clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -604,6 +606,8 @@ vepu_mmu: iommu@ff340800 {
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -613,6 +617,8 @@ vpu_mmu: iommu@ff350800 {
reg = <0x0 0xff350800 0x0 0x40>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -622,6 +628,8 @@ rkvdec_mmu: iommu@ff360480 {
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -631,6 +639,8 @@ vop_mmu: iommu@ff373f00 {
reg = <0x0 0xff373f00 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};

10
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -742,6 +742,8 @@ iep_mmu: iommu@ff900800 {
reg = <0x0 0xff900800 0x0 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -752,6 +754,8 @@ isp_mmu: iommu@ff914000 {
<0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_mmu";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
@ -762,6 +766,8 @@ vop_mmu: iommu@ff930300 {
reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -772,6 +778,8 @@ hevc_mmu: iommu@ff9a0440 {
<0x0 0xff9a0480 0x0 0x40>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -782,6 +790,8 @@ vpu_mmu: iommu@ff9a0800 {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu", "vdpu_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};

8
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
View File

@ -662,6 +662,14 @@ &sdhci {
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;

4
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
View File

@ -255,7 +255,7 @@ digitizer: digitizer@9 {
&ap_i2c_tp {
trackpad@4a {
compatible = "atmel,atmel_mxt_tp";
compatible = "atmel,maxtouch";
reg = <0x4a>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_int_l>;
@ -271,7 +271,7 @@ KEY_RESERVED
&ap_i2c_ts {
touchscreen@4b {
compatible = "atmel,atmel_mxt_ts";
compatible = "atmel,maxtouch";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&touch_int_l>;

8
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View File

@ -588,7 +588,9 @@ &cru {
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>;
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
assigned-clock-rates =
<600000000>, <800000000>,
<1000000000>,
@ -597,7 +599,9 @@ &cru {
<100000000>, <100000000>,
<50000000>, <800000000>,
<100000000>, <50000000>,
<400000000>;
<400000000>, <400000000>,
<200000000>,
<200000000>;
};
&emmc_phy {

25
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
View File

@ -143,6 +143,11 @@ vddd_codec: vddd-codec {
};
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@ -246,6 +251,10 @@ &spi5 {
status = "okay";
};
&tcphy0 {
status = "okay";
};
&u2phy0 {
status = "okay";
};
@ -281,3 +290,19 @@ &usb_host0_ehci {
&usb_host0_ohci {
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
View File

@ -527,6 +527,10 @@ norflash: flash@0 {
};
};
&tcphy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;

12
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
View File

@ -190,6 +190,18 @@ &i2s0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
&pinctrl {
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {

23
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
View File

@ -471,21 +471,6 @@ &io_domains {
gpio1830-supply = <&vcc_3v0>;
};
&pcie_phy {
status = "okay";
};
&pcie0 {
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
@ -560,6 +545,14 @@ &sdmmc {
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;

36
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -312,6 +312,8 @@ sdmmc: dwmmc@fe320000 {
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
max-frequency = <150000000>;
assigned-clocks = <&cru HCLK_SD>;
assigned-clock-rates = <200000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@ -411,8 +413,8 @@ usbdrd_dwc3_0: dwc3 {
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
phys = <&u2phy0_otg>, <&tcphy0_usb3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@ -444,8 +446,8 @@ usbdrd_dwc3_1: dwc3 {
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
phys = <&u2phy1_otg>;
phy-names = "usb2-phy";
phys = <&u2phy1_otg>, <&tcphy1_usb3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@ -461,8 +463,8 @@ cdn_dp: dp@fec00000 {
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
assigned-clock-rates = <100000000>, <200000000>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
@ -1234,6 +1236,8 @@ vpu_mmu: iommu@ff650800 {
reg = <0x0 0xff650800 0x0 0x40>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -1243,6 +1247,8 @@ vdec_mmu: iommu@ff660480 {
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -1252,6 +1258,8 @@ iep_mmu: iommu@ff670800 {
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
};
@ -1323,7 +1331,9 @@ cru: clock-controller@ff760000 {
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
<&cru ACLK_VIO>;
<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
<&cru ACLK_GIC_PRE>,
<&cru PCLK_DDR>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
@ -1332,7 +1342,9 @@ cru: clock-controller@ff760000 {
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>,
<400000000>;
<400000000>, <400000000>,
<200000000>,
<200000000>;
};
grf: syscon@ff770000 {
@ -1599,7 +1611,7 @@ vopl_mmu: iommu@ff8f3f00 {
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "hclk";
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPL>;
#iommu-cells = <0>;
status = "disabled";
@ -1656,7 +1668,7 @@ vopb_mmu: iommu@ff903f00 {
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "hclk";
clock-names = "aclk", "iface";
power-domains = <&power RK3399_PD_VOPB>;
#iommu-cells = <0>;
status = "disabled";
@ -1667,6 +1679,8 @@ isp0_mmu: iommu@ff914000 {
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
@ -1677,6 +1691,8 @@ isp1_mmu: iommu@ff924000 {
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";