mirror of https://gitee.com/openkylin/linux.git
dts changes for mcan for omaps for v4.19 merge window
These changes configure the mcan clock, interconnect target module and mcan device. These changes depend on the ti-sysc related driver changes and are based on those. Notably this is the first new driver that probes with ti-sysc driver with no legacy hwmod platform data for the interconnect target module. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAltGAUURHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXO1eA//fbUztpM4DFjzFqqsesdkkzyEdgYtcMj/ FtP/pntzzSyP7hqGPTLUhK7qrDUbsxXvBu7AfGer57XjU3IzcrHTmMF5gKTo5Dju bM+qZL7xYgTnFVkNvVxjY0dLz14PUPEPIYJEzrZ3njc17jlMvCXyfOVnEe3pZfFz lH2oGmUOJjf05pZCOYqOIxjQM9ggJapHorQ4uM5FHkZSD9T8apoAtmlLlYVTdgkh bEQIpO+37iuL0Ds06tkJ84SRO/l5P5/Q/jCl72lx8H20Yx56ZdN5ca+jCPwzjjJ3 ZuCyTec/8QPRnFS/jOLCtjM+zam37npxkHcuNujV5SghHntifbg7bN1jYBWIttkc +q3dRT/eJYCdjQrR2qp54o1megIJpE4RgbvSCfn2/jBAGZKOeNe799HIao9tCm+W nc62bHUvObHWpMSeyLX8Hi5ywW3UXX7/gCex8oalzL4t+680pTm9/TGZf3WMdwL6 GU+zcvG3uf97dR0eRgTRZX3PBfQyTmU0ACCDNhV0GCUh+p0D/G8U64HiU6ORX6Dy u9DnSGudOZZTKi99PboN+75A9r3wlzxdq0ko5DPMXYgbgzrj4KzONAaMI2PKaktK A7pAqtE8/Dos/e/yonBa0H94Ft1pjccKHR/Z8cRKPb50TbOIViMWWwL/CI2ZkwV0 hcT+iy+MrE0= =v277 -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.19/dt-mcan-v2-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt dts changes for mcan for omaps for v4.19 merge window These changes configure the mcan clock, interconnect target module and mcan device. These changes depend on the ti-sysc related driver changes and are based on those. Notably this is the first new driver that probes with ti-sysc driver with no legacy hwmod platform data for the interconnect target module. * tag 'omap-for-v4.19/dt-mcan-v2-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra76x: Add MCAN node ARM: dts: Add generic interconnect target module node for MCAN ARM: dts: dra762: Add MCAN clock support bus: ti-sysc: Add support for software reset bus: ti-sysc: Add support for using ti-sysc for MCAN on dra76x clk: ti: dra7: Add clkctrl clock data for the mcan clocks bus: ti-sysc: Use 2-factor allocator arguments Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
8291ca5d2a
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@ -36,6 +36,7 @@ Required standard properties:
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"ti,sysc-omap-aes"
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"ti,sysc-mcasp"
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"ti,sysc-usb-host-fs"
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"ti,sysc-dra7-mcan"
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- reg shall have register areas implemented for the interconnect
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target module in question such as revision, sysc and syss
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@ -444,3 +444,9 @@ &extcon_usb1 {
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&extcon_usb2 {
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vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
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};
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&m_can0 {
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can-transceiver {
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max-bitrate = <5000000>;
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};
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};
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@ -11,9 +11,73 @@
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/ {
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compatible = "ti,dra762", "ti,dra7";
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ocp {
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target-module@42c01900 {
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compatible = "ti,sysc-dra7-mcan", "ti,sysc";
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ranges = <0x0 0x42c00000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42c01900 0x4>,
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<0x42c01904 0x4>,
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<0x42c01908 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
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SYSC_DRA7_MCAN_ENAWAKEUP)>;
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ti,syss-mask = <1>;
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clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>;
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clock-names = "fck";
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m_can0: mcan@1a00 {
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compatible = "bosch,m_can";
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reg = <0x1a00 0x4000>, <0x0 0x18FC>;
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reg-names = "m_can", "message_ram";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&mcan_clk>, <&l3_iclk_div>;
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clock-names = "cclk", "hclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
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};
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};
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};
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};
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/* MCAN interrupts are hard-wired to irqs 67, 68 */
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&crossbar_mpu {
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ti,irqs-skip = <10 67 68 133 139 140>;
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};
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&scm_conf_clocks {
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dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_gmac_x2_ck>;
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ti,max-div = <63>;
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reg = <0x03fc>;
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ti,bit-shift=<20>;
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ti,latch-bit=<26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
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assigned-clock-rates = <80000000>;
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};
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dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
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reg = <0x3fc>;
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ti,bit-shift = <29>;
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ti,latch-bit=<26>;
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assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
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};
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mcan_clk: mcan_clk@3fc {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
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ti,bit-shift = <27>;
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reg = <0x3fc>;
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};
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};
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@ -23,11 +23,14 @@
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/iopoll.h>
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#include <linux/platform_data/ti-sysc.h>
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#include <dt-bindings/bus/ti-sysc.h>
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#define MAX_MODULE_SOFTRESET_WAIT 10000
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static const char * const reg_names[] = { "rev", "sysc", "syss", };
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enum sysc_clocks {
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@ -88,6 +91,11 @@ struct sysc {
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struct delayed_work idle_work;
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};
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void sysc_write(struct sysc *ddata, int offset, u32 value)
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{
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writel_relaxed(value, ddata->module_va + offset);
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}
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static u32 sysc_read(struct sysc *ddata, int offset)
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{
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if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
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@ -169,9 +177,9 @@ static int sysc_get_clocks(struct sysc *ddata)
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const char *name;
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int nr_fck = 0, nr_ick = 0, i, error = 0;
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ddata->clock_roles = devm_kzalloc(ddata->dev,
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sizeof(*ddata->clock_roles) *
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ddata->clock_roles = devm_kcalloc(ddata->dev,
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SYSC_MAX_CLOCKS,
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sizeof(*ddata->clock_roles),
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GFP_KERNEL);
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if (!ddata->clock_roles)
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return -ENOMEM;
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@ -200,8 +208,8 @@ static int sysc_get_clocks(struct sysc *ddata)
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return -EINVAL;
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}
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ddata->clocks = devm_kzalloc(ddata->dev,
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sizeof(*ddata->clocks) * ddata->nr_clocks,
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ddata->clocks = devm_kcalloc(ddata->dev,
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ddata->nr_clocks, sizeof(*ddata->clocks),
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GFP_KERNEL);
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if (!ddata->clocks)
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return -ENOMEM;
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@ -943,6 +951,36 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
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}
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}
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static int sysc_reset(struct sysc *ddata)
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{
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int offset = ddata->offsets[SYSC_SYSCONFIG];
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int val;
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if (ddata->legacy_mode || offset < 0 ||
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ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
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return 0;
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/*
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* Currently only support reset status in sysstatus.
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* Warn and return error in all other cases
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*/
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if (!ddata->cfg.syss_mask) {
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dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n");
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return -EINVAL;
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}
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val = sysc_read(ddata, offset);
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val |= (0x1 << ddata->cap->regbits->srst_shift);
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sysc_write(ddata, offset, val);
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/* Poll on reset status */
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offset = ddata->offsets[SYSC_SYSSTATUS];
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return readl_poll_timeout(ddata->module_va + offset, val,
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(val & ddata->cfg.syss_mask) == 0x0,
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100, MAX_MODULE_SOFTRESET_WAIT);
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}
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/* At this point the module is configured enough to read the revision */
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static int sysc_init_module(struct sysc *ddata)
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{
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@ -960,6 +998,14 @@ static int sysc_init_module(struct sysc *ddata)
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return 0;
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}
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error = sysc_reset(ddata);
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if (error) {
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dev_err(ddata->dev, "Reset failed with %d\n", error);
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pm_runtime_put_sync(ddata->dev);
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return error;
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}
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ddata->revision = sysc_read_revision(ddata);
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pm_runtime_put_sync(ddata->dev);
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@ -1552,6 +1598,23 @@ static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
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.regbits = &sysc_regbits_omap4_usb_host_fs,
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};
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static const struct sysc_regbits sysc_regbits_dra7_mcan = {
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.dmadisable_shift = -ENODEV,
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.midle_shift = -ENODEV,
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.sidle_shift = -ENODEV,
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.clkact_shift = -ENODEV,
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.enwkup_shift = 4,
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.srst_shift = 0,
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.emufree_shift = -ENODEV,
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.autoidle_shift = -ENODEV,
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};
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static const struct sysc_capabilities sysc_dra7_mcan = {
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.type = TI_SYSC_DRA7_MCAN,
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.sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
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.regbits = &sysc_regbits_dra7_mcan,
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};
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static int sysc_init_pdata(struct sysc *ddata)
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{
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struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
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@ -1743,6 +1806,7 @@ static const struct of_device_id sysc_match[] = {
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{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
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{ .compatible = "ti,sysc-usb-host-fs",
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.data = &sysc_omap4_usb_host_fs, },
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{ .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sysc_match);
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@ -708,6 +708,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons
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{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
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{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
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{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
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{ DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
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{ 0 },
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};
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@ -15,6 +15,8 @@
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/* SmartReflex sysc found on 36xx and later */
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#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
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#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
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/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
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#define SYSC_IDLE_FORCE 0
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#define SYSC_IDLE_NO 1
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@ -168,5 +168,6 @@
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#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
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#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
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#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
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#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
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#endif
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@ -14,6 +14,7 @@ enum ti_sysc_module_type {
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TI_SYSC_OMAP4_SR,
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TI_SYSC_OMAP4_MCASP,
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TI_SYSC_OMAP4_USB_HOST_FS,
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TI_SYSC_DRA7_MCAN,
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};
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struct ti_sysc_cookie {
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