mirror of https://gitee.com/openkylin/linux.git
arm64: Support systems without FP/ASIMD
The arm64 kernel assumes that FP/ASIMD units are always present and accesses the FP/ASIMD specific registers unconditionally. This could cause problems when they are absent. This patch adds the support for kernel handling systems without FP/ASIMD by skipping the register access within the kernel. For kvm, we trap the accesses to FP/ASIMD and inject an undefined instruction exception to the VM. The callers of the exported kernel_neon_begin_partial() should make sure that the FP/ASIMD is supported. Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> [catalin.marinas@arm.com: add comment on the ARM64_HAS_NO_FPSIMD conflict and the new location] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -38,8 +38,13 @@
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#define ARM64_HAS_32BIT_EL0 13
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#define ARM64_HYP_OFFSET_LOW 14
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#define ARM64_MISMATCHED_CACHE_LINE_SIZE 15
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/*
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* The macro below will be moved to asm/cpucaps.h together with the
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* ARM64_NCAPS update.
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*/
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#define ARM64_HAS_NO_FPSIMD 16
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#define ARM64_NCAPS 16
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#define ARM64_NCAPS 17
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#ifndef __ASSEMBLY__
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@ -231,6 +236,11 @@ static inline bool system_supports_mixed_endian_el0(void)
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return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
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}
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static inline bool system_supports_fpsimd(void)
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{
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return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
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}
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#endif /* __ASSEMBLY__ */
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#endif
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@ -9,8 +9,9 @@
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*/
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#include <linux/types.h>
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#include <asm/fpsimd.h>
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#define cpu_has_neon() (1)
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#define cpu_has_neon() system_supports_fpsimd()
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#define kernel_neon_begin() kernel_neon_begin_partial(32)
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@ -746,6 +746,14 @@ static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
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return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
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}
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static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
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{
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u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1);
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return cpuid_feature_extract_signed_field(pfr0,
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ID_AA64PFR0_FP_SHIFT) < 0;
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}
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static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "GIC system register CPU interface",
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@ -829,6 +837,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.def_scope = SCOPE_SYSTEM,
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.matches = hyp_offset_low,
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},
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{
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/* FP/SIMD is not implemented */
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.capability = ARM64_HAS_NO_FPSIMD,
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.def_scope = SCOPE_SYSTEM,
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.min_field_value = 0,
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.matches = has_no_fpsimd,
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},
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{},
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};
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@ -127,6 +127,8 @@ void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs)
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void fpsimd_thread_switch(struct task_struct *next)
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{
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if (!system_supports_fpsimd())
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return;
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/*
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* Save the current FPSIMD state to memory, but only if whatever is in
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* the registers is in fact the most recent userland FPSIMD state of
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@ -157,6 +159,8 @@ void fpsimd_thread_switch(struct task_struct *next)
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void fpsimd_flush_thread(void)
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{
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if (!system_supports_fpsimd())
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return;
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memset(¤t->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
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fpsimd_flush_task_state(current);
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set_thread_flag(TIF_FOREIGN_FPSTATE);
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@ -168,6 +172,8 @@ void fpsimd_flush_thread(void)
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*/
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void fpsimd_preserve_current_state(void)
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{
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if (!system_supports_fpsimd())
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return;
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preempt_disable();
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if (!test_thread_flag(TIF_FOREIGN_FPSTATE))
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fpsimd_save_state(¤t->thread.fpsimd_state);
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@ -181,6 +187,8 @@ void fpsimd_preserve_current_state(void)
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*/
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void fpsimd_restore_current_state(void)
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{
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if (!system_supports_fpsimd())
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return;
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
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struct fpsimd_state *st = ¤t->thread.fpsimd_state;
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@ -199,6 +207,8 @@ void fpsimd_restore_current_state(void)
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*/
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void fpsimd_update_current_state(struct fpsimd_state *state)
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{
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if (!system_supports_fpsimd())
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return;
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preempt_disable();
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fpsimd_load_state(state);
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if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
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@ -228,6 +238,8 @@ static DEFINE_PER_CPU(struct fpsimd_partial_state, softirq_fpsimdstate);
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*/
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void kernel_neon_begin_partial(u32 num_regs)
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{
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if (WARN_ON(!system_supports_fpsimd()))
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return;
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if (in_interrupt()) {
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struct fpsimd_partial_state *s = this_cpu_ptr(
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in_irq() ? &hardirq_fpsimdstate : &softirq_fpsimdstate);
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@ -252,6 +264,8 @@ EXPORT_SYMBOL(kernel_neon_begin_partial);
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void kernel_neon_end(void)
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{
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if (!system_supports_fpsimd())
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return;
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if (in_interrupt()) {
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struct fpsimd_partial_state *s = this_cpu_ptr(
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in_irq() ? &hardirq_fpsimdstate : &softirq_fpsimdstate);
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@ -57,6 +57,16 @@ static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
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return 1;
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}
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/*
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* Guest access to FP/ASIMD registers are routed to this handler only
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* when the system doesn't support FP/ASIMD.
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*/
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static int handle_no_fpsimd(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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kvm_inject_undefined(vcpu);
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return 1;
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}
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/**
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* kvm_handle_wfx - handle a wait-for-interrupts or wait-for-event
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* instruction executed by a guest
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@ -144,6 +154,7 @@ static exit_handle_fn arm_exit_handlers[] = {
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[ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug,
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[ESR_ELx_EC_BRK64] = kvm_handle_guest_debug,
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[ESR_ELx_EC_FP_ASIMD] = handle_no_fpsimd,
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};
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static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
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@ -106,9 +106,16 @@ el1_trap:
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* x0: ESR_EC
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*/
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/* Guest accessed VFP/SIMD registers, save host, restore Guest */
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/*
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* We trap the first access to the FP/SIMD to save the host context
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* and restore the guest context lazily.
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* If FP/SIMD is not implemented, handle the trap and inject an
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* undefined instruction exception to the guest.
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*/
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alternative_if_not ARM64_HAS_NO_FPSIMD
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cmp x0, #ESR_ELx_EC_FP_ASIMD
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b.eq __fpsimd_guest_restore
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alternative_else_nop_endif
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mrs x1, tpidr_el2
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mov x0, #ARM_EXCEPTION_TRAP
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@ -21,6 +21,7 @@
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#include <asm/fpsimd.h>
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static bool __hyp_text __fpsimd_enabled_nvhe(void)
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{
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@ -76,9 +77,11 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)
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* traps are only taken to EL2 if the operation would not otherwise
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* trap to EL1. Therefore, always make sure that for 32-bit guests,
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* we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
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* If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
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* it will cause an exception.
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*/
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val = vcpu->arch.hcr_el2;
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if (!(val & HCR_RW)) {
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if (!(val & HCR_RW) && system_supports_fpsimd()) {
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write_sysreg(1 << 30, fpexc32_el2);
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isb();
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}
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