mirror of https://gitee.com/openkylin/linux.git
mfd: add DB5500 PRCMU driver
This adds the DB5500 PRCMU driver. Right now this one is pretty restricted in functionality, exposing a simple interface to send I2C messages. Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
3df57bcf5a
commit
8317797ca6
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@ -12,6 +12,7 @@ menu "Ux500 SoC"
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config UX500_SOC_DB5500
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bool "DB5500"
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select MFD_DB5500_PRCMU
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config UX500_SOC_DB8500
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bool "DB8500"
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@ -9,6 +9,7 @@
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/mfd/db8500-prcmu.h>
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#include <linux/mfd/db5500-prcmu.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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@ -49,6 +50,8 @@ void __init ux500_init_irq(void)
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* Init clocks here so that they are available for system timer
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* initialization.
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*/
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if (cpu_is_u5500())
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db5500_prcmu_early_init();
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if (cpu_is_u8500())
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prcmu_early_init();
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clk_init();
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@ -585,6 +585,16 @@ config MFD_DB8500_PRCMU
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system controller running an XP70 microprocessor, which is accessed
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through a register map.
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config MFD_DB5500_PRCMU
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bool "ST-Ericsson DB5500 Power Reset Control Management Unit"
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depends on UX500_SOC_DB5500
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select MFD_CORE
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help
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Select this option to enable support for the DB5500 Power Reset
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and Control Management Unit. This is basically an autonomous
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system controller running an XP70 microprocessor, which is accessed
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through a register map.
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config MFD_CS5535
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tristate "Support for CS5535 and CS5536 southbridge core functions"
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select MFD_CORE
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@ -79,6 +79,7 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o
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obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o
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# ab8500-i2c need to come after db8500-prcmu (which provides the channel)
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obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o
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obj-$(CONFIG_MFD_DB5500_PRCMU) += db5500-prcmu.o
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obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
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obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
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obj-$(CONFIG_LPC_SCH) += lpc_sch.o
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@ -0,0 +1,115 @@
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/*
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* Copyright (C) STMicroelectronics 2009
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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* Author: Sundar Iyer <sundar.iyer@stericsson.com>
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*
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* License Terms: GNU General Public License v2
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*
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* PRCM Unit registers
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*/
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#ifndef __MACH_PRCMU_REGS_H
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#define __MACH_PRCMU_REGS_H
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#include <mach/hardware.h>
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#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
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#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
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#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
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#define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8)
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#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
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#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
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#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1
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#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
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#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
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#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
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#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
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#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
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#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
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#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
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#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
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#define PRCM_IOCR (_PRCMU_BASE + 0x310)
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#define PRCM_IOCR_IOFORCE 0x1
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/* CPU mailbox registers */
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#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
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#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
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#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
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/* Dual A9 core interrupt management unit registers */
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#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
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#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
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#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
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#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
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#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
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#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
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#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
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#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
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#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
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#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
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#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
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#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
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#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
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#define ARM_WAKEUP_MODEM 0x1
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#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
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#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
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#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
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#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
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#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
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#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
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#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
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#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
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#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
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#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
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#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
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/* System reset register */
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#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
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/* Level shifter and clamp control registers */
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#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
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#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
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/* PRCMU clock/PLL/reset registers */
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#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
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#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
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#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
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#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
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#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
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#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
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#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
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#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
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#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
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#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
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#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
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#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
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#define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC)
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/* ePOD and memory power signal control registers */
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#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
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#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
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/* Debug power control unit registers */
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#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
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/* Miscellaneous unit registers */
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#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
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#define PRCM_GPIOCR (_PRCMU_BASE + 0x138)
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#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
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#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
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#endif /* __MACH_PRCMU__REGS_H */
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@ -0,0 +1,448 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
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*
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* U5500 PRCM Unit interface driver
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/completion.h>
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#include <linux/irq.h>
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#include <linux/jiffies.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/db5500-prcmu.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/db5500-regs.h>
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#include "db5500-prcmu-regs.h"
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#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
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#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
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#define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
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#define PRCM_REQ_MB2_HEADER (_PRCM_MB_HEADER + 0x2)
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#define PRCM_REQ_MB3_HEADER (_PRCM_MB_HEADER + 0x3)
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#define PRCM_REQ_MB4_HEADER (_PRCM_MB_HEADER + 0x4)
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#define PRCM_REQ_MB5_HEADER (_PRCM_MB_HEADER + 0x5)
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#define PRCM_REQ_MB6_HEADER (_PRCM_MB_HEADER + 0x6)
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#define PRCM_REQ_MB7_HEADER (_PRCM_MB_HEADER + 0x7)
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#define PRCM_ACK_MB0_HEADER (_PRCM_MB_HEADER + 0x8)
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#define PRCM_ACK_MB1_HEADER (_PRCM_MB_HEADER + 0x9)
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#define PRCM_ACK_MB2_HEADER (_PRCM_MB_HEADER + 0xa)
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#define PRCM_ACK_MB3_HEADER (_PRCM_MB_HEADER + 0xb)
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#define PRCM_ACK_MB4_HEADER (_PRCM_MB_HEADER + 0xc)
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#define PRCM_ACK_MB5_HEADER (_PRCM_MB_HEADER + 0xd)
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#define PRCM_ACK_MB6_HEADER (_PRCM_MB_HEADER + 0xe)
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#define PRCM_ACK_MB7_HEADER (_PRCM_MB_HEADER + 0xf)
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/* Req Mailboxes */
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#define PRCM_REQ_MB0 (tcdm_base + 0xFD8)
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#define PRCM_REQ_MB1 (tcdm_base + 0xFCC)
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#define PRCM_REQ_MB2 (tcdm_base + 0xFC4)
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#define PRCM_REQ_MB3 (tcdm_base + 0xFC0)
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#define PRCM_REQ_MB4 (tcdm_base + 0xF98)
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#define PRCM_REQ_MB5 (tcdm_base + 0xF90)
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#define PRCM_REQ_MB6 (tcdm_base + 0xF8C)
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#define PRCM_REQ_MB7 (tcdm_base + 0xF84)
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/* Ack Mailboxes */
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#define PRCM_ACK_MB0 (tcdm_base + 0xF38)
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#define PRCM_ACK_MB1 (tcdm_base + 0xF30)
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#define PRCM_ACK_MB2 (tcdm_base + 0xF24)
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#define PRCM_ACK_MB3 (tcdm_base + 0xF20)
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#define PRCM_ACK_MB4 (tcdm_base + 0xF1C)
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#define PRCM_ACK_MB5 (tcdm_base + 0xF14)
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#define PRCM_ACK_MB6 (tcdm_base + 0xF0C)
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#define PRCM_ACK_MB7 (tcdm_base + 0xF08)
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enum mb_return_code {
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RC_SUCCESS,
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RC_FAIL,
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};
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/* Mailbox 0 headers. */
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enum mb0_header {
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/* request */
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RMB0H_PWR_STATE_TRANS = 1,
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RMB0H_WAKE_UP_CFG,
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RMB0H_RD_WAKE_UP_ACK,
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/* acknowledge */
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AMB0H_WAKE_UP = 1,
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};
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/* Mailbox 5 headers. */
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enum mb5_header {
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MB5H_I2C_WRITE = 1,
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MB5H_I2C_READ,
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};
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/* Request mailbox 5 fields. */
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#define PRCM_REQ_MB5_I2C_SLAVE (PRCM_REQ_MB5 + 0)
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#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 1)
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#define PRCM_REQ_MB5_I2C_SIZE (PRCM_REQ_MB5 + 2)
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#define PRCM_REQ_MB5_I2C_DATA (PRCM_REQ_MB5 + 4)
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/* Acknowledge mailbox 5 fields. */
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#define PRCM_ACK_MB5_RETURN_CODE (PRCM_ACK_MB5 + 0)
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#define PRCM_ACK_MB5_I2C_DATA (PRCM_ACK_MB5 + 4)
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#define NUM_MB 8
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#define MBOX_BIT BIT
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#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
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/*
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* Used by MCDE to setup all necessary PRCMU registers
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*/
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#define PRCMU_RESET_DSIPLL 0x00004000
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#define PRCMU_UNCLAMP_DSIPLL 0x00400800
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/* HDMI CLK MGT PLLSW=001 (PLLSOC0), PLLDIV=0x8, = 50 Mhz*/
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#define PRCMU_DSI_CLOCK_SETTING 0x00000128
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/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
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#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
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#define PRCMU_PLLDSI_FREQ_SETTING 0x0004013C
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#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
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#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000101
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#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
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#define PRCMU_ENABLE_PLLDSI 0x00000001
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#define PRCMU_DISABLE_PLLDSI 0x00000000
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#define PRCMU_DSI_RESET_SW 0x00000003
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#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
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/*
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* mb0_transfer - state needed for mailbox 0 communication.
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* @lock: The transaction lock.
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*/
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static struct {
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spinlock_t lock;
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} mb0_transfer;
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/*
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* mb5_transfer - state needed for mailbox 5 communication.
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* @lock: The transaction lock.
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* @work: The transaction completion structure.
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* @ack: Reply ("acknowledge") data.
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*/
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static struct {
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struct mutex lock;
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struct completion work;
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struct {
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u8 header;
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u8 status;
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u8 value[4];
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} ack;
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} mb5_transfer;
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/* PRCMU TCDM base IO address. */
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static __iomem void *tcdm_base;
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/**
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* db5500_prcmu_abb_read() - Read register value(s) from the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The read out value(s).
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* @size: The number of registers to read.
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*
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* Reads register value(s) from the ABB.
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* @size has to be <= 4.
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*/
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int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if ((size < 1) || (4 < size))
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return -EINVAL;
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mutex_lock(&mb5_transfer.lock);
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
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writeb(reg, PRCM_REQ_MB5_I2C_REG);
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writeb(size, PRCM_REQ_MB5_I2C_SIZE);
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writeb(MB5H_I2C_READ, PRCM_REQ_MB5_HEADER);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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wait_for_completion(&mb5_transfer.work);
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r = 0;
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if ((mb5_transfer.ack.header == MB5H_I2C_READ) &&
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(mb5_transfer.ack.status == RC_SUCCESS))
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memcpy(value, mb5_transfer.ack.value, (size_t)size);
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else
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r = -EIO;
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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/**
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* db5500_prcmu_abb_write() - Write register value(s) to the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The value(s) to write.
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* @size: The number of registers to write.
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*
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* Writes register value(s) to the ABB.
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* @size has to be <= 4.
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*/
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int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if ((size < 1) || (4 < size))
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return -EINVAL;
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mutex_lock(&mb5_transfer.lock);
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
|
||||
writeb(reg, PRCM_REQ_MB5_I2C_REG);
|
||||
writeb(size, PRCM_REQ_MB5_I2C_SIZE);
|
||||
memcpy_toio(PRCM_REQ_MB5_I2C_DATA, value, size);
|
||||
writeb(MB5H_I2C_WRITE, PRCM_REQ_MB5_HEADER);
|
||||
|
||||
writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
|
||||
wait_for_completion(&mb5_transfer.work);
|
||||
|
||||
if ((mb5_transfer.ack.header == MB5H_I2C_WRITE) &&
|
||||
(mb5_transfer.ack.status == RC_SUCCESS))
|
||||
r = 0;
|
||||
else
|
||||
r = -EIO;
|
||||
|
||||
mutex_unlock(&mb5_transfer.lock);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int db5500_prcmu_enable_dsipll(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Enable DSIPLL_RESETN resets */
|
||||
writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
|
||||
/* Unclamp DSIPLL in/out */
|
||||
writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
|
||||
/* Set DSI PLL FREQ */
|
||||
writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
|
||||
writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
|
||||
PRCM_DSI_PLLOUT_SEL);
|
||||
/* Enable Escape clocks */
|
||||
writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
|
||||
|
||||
/* Start DSI PLL */
|
||||
writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
|
||||
/* Reset DSI PLL */
|
||||
writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
|
||||
for (i = 0; i < 10; i++) {
|
||||
if ((readl(PRCM_PLLDSI_LOCKP) &
|
||||
PRCMU_PLLDSI_LOCKP_LOCKED) == PRCMU_PLLDSI_LOCKP_LOCKED)
|
||||
break;
|
||||
udelay(100);
|
||||
}
|
||||
/* Release DSIPLL_RESETN */
|
||||
writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int db5500_prcmu_disable_dsipll(void)
|
||||
{
|
||||
/* Disable dsi pll */
|
||||
writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
|
||||
/* Disable escapeclock */
|
||||
writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int db5500_prcmu_set_display_clocks(void)
|
||||
{
|
||||
/* HDMI and TVCLK Should be handled somewhere else */
|
||||
/* PLLDIV=8, PLLSW=2, CLKEN=1 */
|
||||
writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
|
||||
/* PLLDIV=14, PLLSW=2, CLKEN=1 */
|
||||
writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ack_dbb_wakeup(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mb0_transfer.lock, flags);
|
||||
|
||||
while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
|
||||
cpu_relax();
|
||||
|
||||
writeb(RMB0H_RD_WAKE_UP_ACK, PRCM_REQ_MB0_HEADER);
|
||||
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
|
||||
|
||||
spin_unlock_irqrestore(&mb0_transfer.lock, flags);
|
||||
}
|
||||
|
||||
static inline void print_unknown_header_warning(u8 n, u8 header)
|
||||
{
|
||||
pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
|
||||
header, n);
|
||||
}
|
||||
|
||||
static bool read_mailbox_0(void)
|
||||
{
|
||||
bool r;
|
||||
u8 header;
|
||||
|
||||
header = readb(PRCM_ACK_MB0_HEADER);
|
||||
switch (header) {
|
||||
case AMB0H_WAKE_UP:
|
||||
r = true;
|
||||
break;
|
||||
default:
|
||||
print_unknown_header_warning(0, header);
|
||||
r = false;
|
||||
break;
|
||||
}
|
||||
writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
|
||||
return r;
|
||||
}
|
||||
|
||||
static bool read_mailbox_1(void)
|
||||
{
|
||||
writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool read_mailbox_2(void)
|
||||
{
|
||||
writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool read_mailbox_3(void)
|
||||
{
|
||||
writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool read_mailbox_4(void)
|
||||
{
|
||||
writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool read_mailbox_5(void)
|
||||
{
|
||||
u8 header;
|
||||
|
||||
header = readb(PRCM_ACK_MB5_HEADER);
|
||||
switch (header) {
|
||||
case MB5H_I2C_READ:
|
||||
memcpy_fromio(mb5_transfer.ack.value, PRCM_ACK_MB5_I2C_DATA, 4);
|
||||
case MB5H_I2C_WRITE:
|
||||
mb5_transfer.ack.header = header;
|
||||
mb5_transfer.ack.status = readb(PRCM_ACK_MB5_RETURN_CODE);
|
||||
complete(&mb5_transfer.work);
|
||||
break;
|
||||
default:
|
||||
print_unknown_header_warning(5, header);
|
||||
break;
|
||||
}
|
||||
writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool read_mailbox_6(void)
|
||||
{
|
||||
writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool read_mailbox_7(void)
|
||||
{
|
||||
writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool (* const read_mailbox[NUM_MB])(void) = {
|
||||
read_mailbox_0,
|
||||
read_mailbox_1,
|
||||
read_mailbox_2,
|
||||
read_mailbox_3,
|
||||
read_mailbox_4,
|
||||
read_mailbox_5,
|
||||
read_mailbox_6,
|
||||
read_mailbox_7
|
||||
};
|
||||
|
||||
static irqreturn_t prcmu_irq_handler(int irq, void *data)
|
||||
{
|
||||
u32 bits;
|
||||
u8 n;
|
||||
irqreturn_t r;
|
||||
|
||||
bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
|
||||
if (unlikely(!bits))
|
||||
return IRQ_NONE;
|
||||
|
||||
r = IRQ_HANDLED;
|
||||
for (n = 0; bits; n++) {
|
||||
if (bits & MBOX_BIT(n)) {
|
||||
bits -= MBOX_BIT(n);
|
||||
if (read_mailbox[n]())
|
||||
r = IRQ_WAKE_THREAD;
|
||||
}
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
|
||||
{
|
||||
ack_dbb_wakeup();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void __init db5500_prcmu_early_init(void)
|
||||
{
|
||||
tcdm_base = __io_address(U5500_PRCMU_TCDM_BASE);
|
||||
spin_lock_init(&mb0_transfer.lock);
|
||||
mutex_init(&mb5_transfer.lock);
|
||||
init_completion(&mb5_transfer.work);
|
||||
}
|
||||
|
||||
/**
|
||||
* prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
|
||||
*
|
||||
*/
|
||||
int __init db5500_prcmu_init(void)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
if (ux500_is_svp() || !cpu_is_u5500())
|
||||
return -ENODEV;
|
||||
|
||||
/* Clean up the mailbox interrupts after pre-kernel code. */
|
||||
writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR);
|
||||
|
||||
r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
|
||||
prcmu_irq_thread_fn, 0, "prcmu", NULL);
|
||||
if (r < 0) {
|
||||
pr_err("prcmu: Failed to allocate IRQ_DB5500_PRCMU1.\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(db5500_prcmu_init);
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
*
|
||||
* License Terms: GNU General Public License v2
|
||||
*
|
||||
* U5500 PRCMU API.
|
||||
*/
|
||||
#ifndef __MACH_PRCMU_U5500_H
|
||||
#define __MACH_PRCMU_U5500_H
|
||||
|
||||
#ifdef CONFIG_UX500_SOC_DB5500
|
||||
|
||||
void db5500_prcmu_early_init(void);
|
||||
|
||||
int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
|
||||
int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
|
||||
|
||||
#else /* !CONFIG_UX500_SOC_DB5500 */
|
||||
|
||||
static inline void db5500_prcmu_early_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_UX500_SOC_DB5500 */
|
||||
|
||||
static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
|
||||
{
|
||||
#ifdef CONFIG_MACH_U5500_SIMULATOR
|
||||
return 0;
|
||||
#else
|
||||
return -1;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* __MACH_PRCMU_U5500_H */
|
||||
Loading…
Reference in New Issue