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clk: exynos5433: Extend list of available AUD_PLL output frequencies 

Add one more entry to the exynos5433_aud_pll_rates table, this allows
to support audio sample rates: 48000, 96000, 192000 Hz with minimum
error. The M, P, S, K values re confirmed by the HW team.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
This commit is contained in:
Sylwester Nawrocki 2018-02-12 16:52:27 +01:00
parent 5c7979246e
commit 83942bdd99
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/samsung/clk-exynos5433.c
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@ -765,6 +765,7 @@ static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initcons
PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),
{ /* sentinel */ }
};