mirror of https://gitee.com/openkylin/linux.git
drm/i915/icl: Fix DDI/TC port clk_off bits
DDI/TC clock-off bits are not equally distanced. TC1-3 bits are from offset 12 & TC4 is at offset 21. Create a function to choose correct clk-off bit. v2: Add fixes tag (Lucas) Fixes:c27e917e2b
("drm/i915/icl: add basic support for the ICL clocks") Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181016023752.9285-1-lucas.demarchi@intel.com (cherry picked from commitbb1c7edc6d
) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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@ -9339,6 +9339,9 @@ enum skl_power_gate {
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#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
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#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
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(port) + 10))
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#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
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#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
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21 : (tc_port) + 12))
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#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
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(port) * 2)
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#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
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@ -2733,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
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return DDI_BUF_TRANS_SELECT(level);
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}
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static inline
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uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
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enum port port)
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{
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if (intel_port_is_combophy(dev_priv, port)) {
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return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
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} else if (intel_port_is_tc(dev_priv, port)) {
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enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
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return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
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}
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return 0;
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}
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void icl_map_plls_to_ports(struct drm_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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struct drm_atomic_state *old_state)
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@ -2756,7 +2771,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
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mutex_lock(&dev_priv->dpll_lock);
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val = I915_READ(DPCLKA_CFGCR0_ICL);
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WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
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WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
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if (intel_port_is_combophy(dev_priv, port)) {
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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@ -2765,7 +2780,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
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POSTING_READ(DPCLKA_CFGCR0_ICL);
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}
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val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
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val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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mutex_unlock(&dev_priv->dpll_lock);
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@ -2793,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
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mutex_lock(&dev_priv->dpll_lock);
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I915_WRITE(DPCLKA_CFGCR0_ICL,
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I915_READ(DPCLKA_CFGCR0_ICL) |
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DPCLKA_CFGCR0_DDI_CLK_OFF(port));
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icl_dpclka_cfgcr0_clk_off(dev_priv, port));
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mutex_unlock(&dev_priv->dpll_lock);
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}
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}
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