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MIPS: Emulate the new MIPS R6 branch compact (BC) instruction 

MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras 2014-11-26 13:56:51 +00:00
parent f1b44067c1
commit 8467ca0122
3 changed files with 23 additions and 1 deletions
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2
arch/mips/include/uapi/asm/inst.h
View File

@ -31,7 +31,7 @@ enum major_op {
lbu_op, lhu_op, lwr_op, lwu_op, lbu_op, lhu_op, lwr_op, lwu_op,
sb_op, sh_op, swl_op, sw_op, sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op, sdl_op, sdr_op, swr_op, cache_op,
ll_op, lwc1_op, lwc2_op, pref_op, ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
lld_op, ldc1_op, ldc2_op, ld_op, lld_op, ldc1_op, ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, major_3b_op, sc_op, swc1_op, swc2_op, major_3b_op,
scd_op, sdc1_op, sdc2_op, sd_op scd_op, sdc1_op, sdc2_op, sd_op

9
arch/mips/kernel/branch.c
View File

@ -780,6 +780,15 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
epc += 8; epc += 8;
regs->cp0_epc = epc; regs->cp0_epc = epc;
break; break;
#else
case bc6_op:
/* Only valid for MIPS R6 */
if (!cpu_has_mips_r6) {
ret = -SIGILL;
break;
}
regs->cp0_epc += 8;
break;
#endif #endif
} }

13
arch/mips/math-emu/cp1emu.c
View File

@ -648,6 +648,19 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
else else
*contpc = regs->cp0_epc + 8; *contpc = regs->cp0_epc + 8;
return 1; return 1;
#else
case bc6_op:
/*
* Only valid for MIPS R6 but we can still end up
* here from a broken userland so just tell emulator
* this is not a branch and let it break later on.
*/
if (!cpu_has_mips_r6)
break;
*contpc = regs->cp0_epc + dec_insn.pc_inc +
dec_insn.next_pc_inc;
return 1;
#endif #endif
case cop0_op: case cop0_op:
case cop1_op: case cop1_op: