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i.MX ehci platform support: Some fixes 

- The SIC mask is only 2bits wide, not 4
- MX31_OTG_PM_BIT and MX31_H1_PM_BIT use negative logic
- clear MX31_H1_DT_BIT and MX31_H2_DT_BIT so that they can be cleared,
  not only set.
- return -EINVAL if called with an invalid controller number

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Daniel Mack <daniel@caiaq.de>
This commit is contained in:
Sascha Hauer 2010-02-04 14:45:11 +01:00
parent ba593e5966
commit 84ab80616b
1 changed files with 9 additions and 7 deletions
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16
arch/arm/plat-mxc/ehci.c
View File

@ -25,16 +25,16 @@
#define USBCTRL_OTGBASE_OFFSET 0x600 #define USBCTRL_OTGBASE_OFFSET 0x600
#define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_SHIFT 29
#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
#define MX31_OTG_PM_BIT (1 << 24) #define MX31_OTG_PM_BIT (1 << 24)
#define MX31_H2_SIC_SHIFT 21 #define MX31_H2_SIC_SHIFT 21
#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
#define MX31_H2_PM_BIT (1 << 16) #define MX31_H2_PM_BIT (1 << 16)
#define MX31_H2_DT_BIT (1 << 5) #define MX31_H2_DT_BIT (1 << 5)
#define MX31_H1_SIC_SHIFT 13 #define MX31_H1_SIC_SHIFT 13
#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
#define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_PM_BIT (1 << 8)
#define MX31_H1_DT_BIT (1 << 4) #define MX31_H1_DT_BIT (1 << 4)
@ -51,15 +51,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_OTG_SIC_SHIFT; << MX31_OTG_SIC_SHIFT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_OTG_PM_BIT; v |= MX31_OTG_PM_BIT;
break; break;
case 1: /* H1 port */ case 1: /* H1 port */
v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_H1_SIC_SHIFT; << MX31_H1_SIC_SHIFT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED) if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX31_H1_PM_BIT; v |= MX31_H1_PM_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED)) if (!(flags & MXC_EHCI_TTL_ENABLED))
@ -67,7 +67,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
break; break;
case 2: /* H2 port */ case 2: /* H2 port */
v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) v |= (flags & MXC_EHCI_INTERFACE_MASK)
<< MX31_H2_SIC_SHIFT; << MX31_H2_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
@ -77,6 +77,8 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
v |= MX31_H2_DT_BIT; v |= MX31_H2_DT_BIT;
break; break;
default:
return -EINVAL;
} }
writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +