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media: dt-bindings: media: nxp,imx7-mipi-csi2: Add i.MX8MM support
The i.MX8MM integrates a newer version of the CSIS CSI-2 receiver as the i.MX7 family. Differences in integration are are: - An additional clock is required - Up to 4 data lanes are supported - No reset or PHY supply is present Support it in the DT binding. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rui Miguel Silva <rmfrfs@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
acdff8e14a
commit
85b62ff2cb
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@ -4,15 +4,17 @@
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$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX7 MIPI CSI-2 receiver
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title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
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maintainers:
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- Rui Miguel Silva <rmfrfs@gmail.com>
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- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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description: |-
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The NXP i.MX7 SoC family includes a MIPI CSI-2 receiver IP core, documented
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as "CSIS V3.3". The IP core seems to originate from Samsung, and may be
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compatible with some of the Exynos4 ad S5P SoCs.
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The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
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receiver IP core named CSIS. The IP core originates from Samsung, and may be
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compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
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3.3, and i.MX8 SoCs use CSIS version 3.6.3.
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While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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completely wrapped by the CSIS and doesn't expose a control interface of its
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@ -20,7 +22,9 @@ description: |-
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properties:
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compatible:
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const: fsl,imx7-mipi-csi2
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enum:
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- fsl,imx7-mipi-csi2
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- fsl,imx8mm-mipi-csi2
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reg:
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maxItems: 1
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@ -29,16 +33,20 @@ properties:
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maxItems: 1
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clocks:
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minItems: 3
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items:
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- description: The peripheral clock (a.k.a. APB clock)
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- description: The external clock (optionally used as the pixel clock)
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- description: The MIPI D-PHY clock
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- description: The AXI clock
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clock-names:
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minItems: 3
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items:
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- const: pclk
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- const: wrap
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- const: phy
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- const: axi
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power-domains:
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maxItems: 1
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@ -71,16 +79,30 @@ properties:
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properties:
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data-lanes:
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oneOf:
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- items:
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- const: 1
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- items:
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- const: 1
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- const: 2
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items:
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minItems: 1
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maxItems: 4
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items:
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- const: 1
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- const: 2
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- const: 3
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- const: 4
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required:
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- data-lanes
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx7-mipi-csi2
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then:
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properties:
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data-lanes:
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items:
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maxItems: 2
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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@ -93,12 +115,29 @@ required:
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- clocks
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- clock-names
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- power-domains
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- phy-supply
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- resets
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- ports
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx7-mipi-csi2
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then:
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required:
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- phy-supply
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- resets
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else:
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properties:
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clocks:
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minItems: 4
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clock-names:
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minItems: 4
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phy-supply: false
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resets: false
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examples:
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- |
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#include <dt-bindings/clock/imx7d-clock.h>
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@ -106,7 +145,7 @@ examples:
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/reset/imx7-reset.h>
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mipi_csi: mipi-csi@30750000 {
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mipi-csi@30750000 {
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compatible = "fsl,imx7-mipi-csi2";
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reg = <0x30750000 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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@ -144,4 +183,46 @@ examples:
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};
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};
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- |
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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mipi-csi@32e30000 {
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compatible = "fsl,imx8mm-mipi-csi2";
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reg = <0x32e30000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <333000000>;
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clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
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<&clk IMX8MM_CLK_CSI1_ROOT>,
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<&clk IMX8MM_CLK_CSI1_PHY_REF>,
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<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
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clock-names = "pclk", "wrap", "phy", "axi";
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power-domains = <&mipi_pd>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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imx8mm_mipi_csi_in: endpoint {
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remote-endpoint = <&imx477_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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imx8mm_mipi_csi_out: endpoint {
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remote-endpoint = <&csi_in>;
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};
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};
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};
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};
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...
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