mirror of https://gitee.com/openkylin/linux.git
pinctrl: freescale: Add imx8mm pinctrl driver support
Add the pinctrl driver support for i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Bai Ping
Linus Walleij
parent
b71c184412
commit
85e4e6881d
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@ -122,6 +122,13 @@ config PINCTRL_IMX7ULP
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help
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Say Y here to enable the imx7ulp pinctrl driver
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config PINCTRL_IMX8MM
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bool "IMX8MM pinctrl driver"
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depends on ARCH_MXC && ARM64
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select PINCTRL_IMX
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help
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Say Y here to enable the imx8mm pinctrl driver
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config PINCTRL_IMX8MQ
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bool "IMX8MQ pinctrl driver"
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depends on ARCH_MXC && ARM64
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@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
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obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
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obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
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obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
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obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
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obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
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obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
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obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
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@ -0,0 +1,348 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2017-2018 NXP
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/platform_device.h>
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#include "pinctrl-imx.h"
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enum imx8mm_pads {
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MX8MM_PAD_RESERVE0 = 0,
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MX8MM_PAD_RESERVE1 = 1,
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MX8MM_PAD_RESERVE2 = 2,
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MX8MM_PAD_RESERVE3 = 3,
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MX8MM_PAD_RESERVE4 = 4,
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MX8MM_PAD_RESERVE5 = 5,
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MX8MM_PAD_RESERVE6 = 6,
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MX8MM_PAD_RESERVE7 = 7,
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MX8MM_PAD_RESERVE8 = 8,
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MX8MM_PAD_RESERVE9 = 9,
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MX8MM_IOMUXC_GPIO1_IO00 = 10,
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MX8MM_IOMUXC_GPIO1_IO01 = 11,
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MX8MM_IOMUXC_GPIO1_IO02 = 12,
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MX8MM_IOMUXC_GPIO1_IO03 = 13,
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MX8MM_IOMUXC_GPIO1_IO04 = 14,
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MX8MM_IOMUXC_GPIO1_IO05 = 15,
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MX8MM_IOMUXC_GPIO1_IO06 = 16,
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MX8MM_IOMUXC_GPIO1_IO07 = 17,
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MX8MM_IOMUXC_GPIO1_IO08 = 18,
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MX8MM_IOMUXC_GPIO1_IO09 = 19,
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MX8MM_IOMUXC_GPIO1_IO10 = 20,
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MX8MM_IOMUXC_GPIO1_IO11 = 21,
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MX8MM_IOMUXC_GPIO1_IO12 = 22,
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MX8MM_IOMUXC_GPIO1_IO13 = 23,
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MX8MM_IOMUXC_GPIO1_IO14 = 24,
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MX8MM_IOMUXC_GPIO1_IO15 = 25,
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MX8MM_IOMUXC_ENET_MDC = 26,
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MX8MM_IOMUXC_ENET_MDIO = 27,
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MX8MM_IOMUXC_ENET_TD3 = 28,
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MX8MM_IOMUXC_ENET_TD2 = 29,
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MX8MM_IOMUXC_ENET_TD1 = 30,
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MX8MM_IOMUXC_ENET_TD0 = 31,
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MX8MM_IOMUXC_ENET_TX_CTL = 32,
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MX8MM_IOMUXC_ENET_TXC = 33,
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MX8MM_IOMUXC_ENET_RX_CTL = 34,
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MX8MM_IOMUXC_ENET_RXC = 35,
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MX8MM_IOMUXC_ENET_RD0 = 36,
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MX8MM_IOMUXC_ENET_RD1 = 37,
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MX8MM_IOMUXC_ENET_RD2 = 38,
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MX8MM_IOMUXC_ENET_RD3 = 39,
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MX8MM_IOMUXC_SD1_CLK = 40,
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MX8MM_IOMUXC_SD1_CMD = 41,
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MX8MM_IOMUXC_SD1_DATA0 = 42,
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MX8MM_IOMUXC_SD1_DATA1 = 43,
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MX8MM_IOMUXC_SD1_DATA2 = 44,
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MX8MM_IOMUXC_SD1_DATA3 = 45,
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MX8MM_IOMUXC_SD1_DATA4 = 46,
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MX8MM_IOMUXC_SD1_DATA5 = 47,
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MX8MM_IOMUXC_SD1_DATA6 = 48,
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MX8MM_IOMUXC_SD1_DATA7 = 49,
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MX8MM_IOMUXC_SD1_RESET_B = 50,
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MX8MM_IOMUXC_SD1_STROBE = 51,
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MX8MM_IOMUXC_SD2_CD_B = 52,
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MX8MM_IOMUXC_SD2_CLK = 53,
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MX8MM_IOMUXC_SD2_CMD = 54,
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MX8MM_IOMUXC_SD2_DATA0 = 55,
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MX8MM_IOMUXC_SD2_DATA1 = 56,
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MX8MM_IOMUXC_SD2_DATA2 = 57,
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MX8MM_IOMUXC_SD2_DATA3 = 58,
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MX8MM_IOMUXC_SD2_RESET_B = 59,
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MX8MM_IOMUXC_SD2_WP = 60,
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MX8MM_IOMUXC_NAND_ALE = 61,
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MX8MM_IOMUXC_NAND_CE0 = 62,
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MX8MM_IOMUXC_NAND_CE1 = 63,
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MX8MM_IOMUXC_NAND_CE2 = 64,
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MX8MM_IOMUXC_NAND_CE3 = 65,
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MX8MM_IOMUXC_NAND_CLE = 66,
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MX8MM_IOMUXC_NAND_DATA00 = 67,
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MX8MM_IOMUXC_NAND_DATA01 = 68,
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MX8MM_IOMUXC_NAND_DATA02 = 69,
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MX8MM_IOMUXC_NAND_DATA03 = 70,
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MX8MM_IOMUXC_NAND_DATA04 = 71,
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MX8MM_IOMUXC_NAND_DATA05 = 72,
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MX8MM_IOMUXC_NAND_DATA06 = 73,
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MX8MM_IOMUXC_NAND_DATA07 = 74,
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MX8MM_IOMUXC_NAND_DQS = 75,
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MX8MM_IOMUXC_NAND_RE_B = 76,
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MX8MM_IOMUXC_NAND_READY_B = 77,
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MX8MM_IOMUXC_NAND_WE_B = 78,
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MX8MM_IOMUXC_NAND_WP_B = 79,
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MX8MM_IOMUXC_SAI5_RXFS = 80,
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MX8MM_IOMUXC_SAI5_RXC = 81,
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MX8MM_IOMUXC_SAI5_RXD0 = 82,
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MX8MM_IOMUXC_SAI5_RXD1 = 83,
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MX8MM_IOMUXC_SAI5_RXD2 = 84,
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MX8MM_IOMUXC_SAI5_RXD3 = 85,
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MX8MM_IOMUXC_SAI5_MCLK = 86,
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MX8MM_IOMUXC_SAI1_RXFS = 87,
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MX8MM_IOMUXC_SAI1_RXC = 88,
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MX8MM_IOMUXC_SAI1_RXD0 = 89,
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MX8MM_IOMUXC_SAI1_RXD1 = 90,
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MX8MM_IOMUXC_SAI1_RXD2 = 91,
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MX8MM_IOMUXC_SAI1_RXD3 = 92,
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MX8MM_IOMUXC_SAI1_RXD4 = 93,
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MX8MM_IOMUXC_SAI1_RXD5 = 94,
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MX8MM_IOMUXC_SAI1_RXD6 = 95,
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MX8MM_IOMUXC_SAI1_RXD7 = 96,
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MX8MM_IOMUXC_SAI1_TXFS = 97,
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MX8MM_IOMUXC_SAI1_TXC = 98,
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MX8MM_IOMUXC_SAI1_TXD0 = 99,
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MX8MM_IOMUXC_SAI1_TXD1 = 100,
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MX8MM_IOMUXC_SAI1_TXD2 = 101,
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MX8MM_IOMUXC_SAI1_TXD3 = 102,
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MX8MM_IOMUXC_SAI1_TXD4 = 103,
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MX8MM_IOMUXC_SAI1_TXD5 = 104,
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MX8MM_IOMUXC_SAI1_TXD6 = 105,
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MX8MM_IOMUXC_SAI1_TXD7 = 106,
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MX8MM_IOMUXC_SAI1_MCLK = 107,
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MX8MM_IOMUXC_SAI2_RXFS = 108,
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MX8MM_IOMUXC_SAI2_RXC = 109,
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MX8MM_IOMUXC_SAI2_RXD0 = 110,
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MX8MM_IOMUXC_SAI2_TXFS = 111,
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MX8MM_IOMUXC_SAI2_TXC = 112,
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MX8MM_IOMUXC_SAI2_TXD0 = 113,
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MX8MM_IOMUXC_SAI2_MCLK = 114,
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MX8MM_IOMUXC_SAI3_RXFS = 115,
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MX8MM_IOMUXC_SAI3_RXC = 116,
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MX8MM_IOMUXC_SAI3_RXD = 117,
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MX8MM_IOMUXC_SAI3_TXFS = 118,
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MX8MM_IOMUXC_SAI3_TXC = 119,
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MX8MM_IOMUXC_SAI3_TXD = 120,
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MX8MM_IOMUXC_SAI3_MCLK = 121,
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MX8MM_IOMUXC_SPDIF_TX = 122,
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MX8MM_IOMUXC_SPDIF_RX = 123,
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MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
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MX8MM_IOMUXC_ECSPI1_SCLK = 125,
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MX8MM_IOMUXC_ECSPI1_MOSI = 126,
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MX8MM_IOMUXC_ECSPI1_MISO = 127,
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MX8MM_IOMUXC_ECSPI1_SS0 = 128,
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MX8MM_IOMUXC_ECSPI2_SCLK = 129,
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MX8MM_IOMUXC_ECSPI2_MOSI = 130,
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MX8MM_IOMUXC_ECSPI2_MISO = 131,
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MX8MM_IOMUXC_ECSPI2_SS0 = 132,
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MX8MM_IOMUXC_I2C1_SCL = 133,
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MX8MM_IOMUXC_I2C1_SDA = 134,
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MX8MM_IOMUXC_I2C2_SCL = 135,
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MX8MM_IOMUXC_I2C2_SDA = 136,
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MX8MM_IOMUXC_I2C3_SCL = 137,
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MX8MM_IOMUXC_I2C3_SDA = 138,
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MX8MM_IOMUXC_I2C4_SCL = 139,
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MX8MM_IOMUXC_I2C4_SDA = 140,
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MX8MM_IOMUXC_UART1_RXD = 141,
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MX8MM_IOMUXC_UART1_TXD = 142,
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MX8MM_IOMUXC_UART2_RXD = 143,
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MX8MM_IOMUXC_UART2_TXD = 144,
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MX8MM_IOMUXC_UART3_RXD = 145,
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MX8MM_IOMUXC_UART3_TXD = 146,
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MX8MM_IOMUXC_UART4_RXD = 147,
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MX8MM_IOMUXC_UART4_TXD = 148,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
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IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
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IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
|
||||
IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
|
||||
};
|
||||
|
||||
static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
|
||||
.pins = imx8mm_pinctrl_pads,
|
||||
.npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
|
||||
.gpr_compatible = "fsl,imx8mm-iomuxc-gpr",
|
||||
};
|
||||
|
||||
static const struct of_device_id imx8mm_pinctrl_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int imx8mm_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info);
|
||||
}
|
||||
|
||||
static struct platform_driver imx8mm_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "imx8mm-pinctrl",
|
||||
.of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = imx8mm_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init imx8mm_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx8mm_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(imx8mm_pinctrl_init);
|
||||
Loading…
Reference in New Issue