mirror of https://gitee.com/openkylin/linux.git
OMAP: DSS2: Represent DISPC register defines with channel as parameter
On OMAP4, we have a new DISPC channel for Overlay Manager LCD2. There is a set of regsiters for LCD2 channel similar to the existing LCD channel, like DISPC_CONTROL2, DISPC_DIVISOR2, DISPC_CONFIG2 and so on. Introduce new enum members for LCD2 Channel and corresponding Overlay Manager in display.h. Represent the following DISPC register defines with channel as a parameter to differentiate between LCD and LCD2 registers (and also DIGIT in some cases): DISPC_DEFAULT_COLOR, DISPC_TRANS_COLOR, DISPC_TIMING_H, DISPC_TIMING_V, DISPC_POL_FREQ, DISPC_DIVISOR, DISPC_SIZE_LCD, DISPC_DATA_CYCLEk, DISPC_CPR_COEF_R, DISPC_CPR_COEF_G and DISPC_CPR_COEF_B This parametrization helps in reducing the number of register defines for DISPC. Replace the existing reads/writes to these registers in this new way. Also, Introduce defines for registers DISPC_CONTROL2 and DISPC_CONFIG2 which are used exclusively for LCD2 channel. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Mukund Mittal <mmittal@ti.com> Signed-off-by: Samreen <samreen@ti.com> Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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@ -64,6 +64,7 @@ enum omap_plane {
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enum omap_channel {
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OMAP_DSS_CHANNEL_LCD = 0,
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OMAP_DSS_CHANNEL_DIGIT = 1,
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OMAP_DSS_CHANNEL_LCD2 = 2,
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};
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enum omap_color_mode {
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@ -142,6 +143,7 @@ enum omap_dss_display_state {
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enum omap_dss_overlay_managers {
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OMAP_DSS_OVL_MGR_LCD,
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OMAP_DSS_OVL_MGR_TV,
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OMAP_DSS_OVL_MGR_LCD2,
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};
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enum omap_dss_rotation_type {
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@ -44,34 +44,40 @@
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/* DISPC */
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#define DISPC_BASE 0x48050400
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#define DISPC_SZ_REGS SZ_1K
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#define DISPC_SZ_REGS SZ_4K
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struct dispc_reg { u16 idx; };
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#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
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/* DISPC common */
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/*
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* DISPC common registers and
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* DISPC channel registers , ch = 0 for LCD, ch = 1 for
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* DIGIT, and ch = 2 for LCD2
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*/
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#define DISPC_REVISION DISPC_REG(0x0000)
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#define DISPC_SYSCONFIG DISPC_REG(0x0010)
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#define DISPC_SYSSTATUS DISPC_REG(0x0014)
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#define DISPC_IRQSTATUS DISPC_REG(0x0018)
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#define DISPC_IRQENABLE DISPC_REG(0x001C)
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#define DISPC_CONTROL DISPC_REG(0x0040)
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#define DISPC_CONTROL2 DISPC_REG(0x0238)
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#define DISPC_CONFIG DISPC_REG(0x0044)
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#define DISPC_CONFIG2 DISPC_REG(0x0620)
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#define DISPC_CAPABLE DISPC_REG(0x0048)
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#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
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#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
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#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
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#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
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#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
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(ch == 1 ? 0x0050 : 0x03AC))
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#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
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(ch == 1 ? 0x0058 : 0x03B0))
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#define DISPC_LINE_STATUS DISPC_REG(0x005C)
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#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
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#define DISPC_TIMING_H DISPC_REG(0x0064)
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#define DISPC_TIMING_V DISPC_REG(0x0068)
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#define DISPC_POL_FREQ DISPC_REG(0x006C)
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#define DISPC_DIVISOR DISPC_REG(0x0070)
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#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
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#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
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#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
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#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
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#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
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#define DISPC_SIZE_DIG DISPC_REG(0x0078)
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#define DISPC_SIZE_LCD DISPC_REG(0x007C)
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#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
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/* DISPC GFX plane */
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#define DISPC_GFX_BA0 DISPC_REG(0x0080)
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@ -86,13 +92,12 @@ struct dispc_reg { u16 idx; };
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#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
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#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
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#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
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#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
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#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
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#define DISPC_CPR_COEF_R DISPC_REG(0x0220)
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#define DISPC_CPR_COEF_G DISPC_REG(0x0224)
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#define DISPC_CPR_COEF_B DISPC_REG(0x0228)
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#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
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#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
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#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
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#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
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#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
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#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
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#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
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@ -217,18 +222,18 @@ void dispc_save_context(void)
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SR(IRQENABLE);
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SR(CONTROL);
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SR(CONFIG);
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SR(DEFAULT_COLOR0);
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SR(DEFAULT_COLOR1);
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SR(TRANS_COLOR0);
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SR(TRANS_COLOR1);
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SR(DEFAULT_COLOR(0));
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SR(DEFAULT_COLOR(1));
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SR(TRANS_COLOR(0));
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SR(TRANS_COLOR(1));
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SR(LINE_NUMBER);
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SR(TIMING_H);
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SR(TIMING_V);
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SR(POL_FREQ);
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SR(DIVISOR);
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SR(TIMING_H(0));
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SR(TIMING_V(0));
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SR(POL_FREQ(0));
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SR(DIVISOR(0));
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SR(GLOBAL_ALPHA);
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SR(SIZE_DIG);
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SR(SIZE_LCD);
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SR(SIZE_LCD(0));
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SR(GFX_BA0);
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SR(GFX_BA1);
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@ -241,13 +246,13 @@ void dispc_save_context(void)
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SR(GFX_WINDOW_SKIP);
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SR(GFX_TABLE_BA);
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SR(DATA_CYCLE1);
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SR(DATA_CYCLE2);
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SR(DATA_CYCLE3);
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SR(DATA_CYCLE1(0));
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SR(DATA_CYCLE2(0));
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SR(DATA_CYCLE3(0));
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SR(CPR_COEF_R);
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SR(CPR_COEF_G);
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SR(CPR_COEF_B);
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SR(CPR_COEF_R(0));
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SR(CPR_COEF_G(0));
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SR(CPR_COEF_B(0));
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SR(GFX_PRELOAD);
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@ -356,18 +361,18 @@ void dispc_restore_context(void)
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/*RR(IRQENABLE);*/
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/*RR(CONTROL);*/
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RR(CONFIG);
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RR(DEFAULT_COLOR0);
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RR(DEFAULT_COLOR1);
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RR(TRANS_COLOR0);
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RR(TRANS_COLOR1);
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RR(DEFAULT_COLOR(0));
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RR(DEFAULT_COLOR(1));
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RR(TRANS_COLOR(0));
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RR(TRANS_COLOR(1));
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RR(LINE_NUMBER);
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RR(TIMING_H);
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RR(TIMING_V);
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RR(POL_FREQ);
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RR(DIVISOR);
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RR(TIMING_H(0));
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RR(TIMING_V(0));
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RR(POL_FREQ(0));
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RR(DIVISOR(0));
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RR(GLOBAL_ALPHA);
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RR(SIZE_DIG);
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RR(SIZE_LCD);
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RR(SIZE_LCD(0));
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RR(GFX_BA0);
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RR(GFX_BA1);
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@ -380,13 +385,13 @@ void dispc_restore_context(void)
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RR(GFX_WINDOW_SKIP);
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RR(GFX_TABLE_BA);
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RR(DATA_CYCLE1);
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RR(DATA_CYCLE2);
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RR(DATA_CYCLE3);
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RR(DATA_CYCLE1(0));
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RR(DATA_CYCLE2(0));
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RR(DATA_CYCLE3(0));
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RR(CPR_COEF_R);
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RR(CPR_COEF_G);
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RR(CPR_COEF_B);
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RR(CPR_COEF_R(0));
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RR(CPR_COEF_G(0));
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RR(CPR_COEF_B(0));
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RR(GFX_PRELOAD);
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@ -942,7 +947,7 @@ void dispc_set_lcd_size(u16 width, u16 height)
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BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
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val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
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enable_clocks(1);
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dispc_write_reg(DISPC_SIZE_LCD, val);
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dispc_write_reg(DISPC_SIZE_LCD(OMAP_DSS_CHANNEL_LCD), val);
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enable_clocks(0);
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}
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@ -1879,25 +1884,20 @@ void dispc_set_loadmode(enum omap_dss_load_mode mode)
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void dispc_set_default_color(enum omap_channel channel, u32 color)
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{
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const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
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DISPC_DEFAULT_COLOR1 };
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enable_clocks(1);
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dispc_write_reg(def_reg[channel], color);
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dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
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enable_clocks(0);
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}
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u32 dispc_get_default_color(enum omap_channel channel)
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{
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const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
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DISPC_DEFAULT_COLOR1 };
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u32 l;
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BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
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channel != OMAP_DSS_CHANNEL_LCD);
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enable_clocks(1);
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l = dispc_read_reg(def_reg[channel]);
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l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
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enable_clocks(0);
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return l;
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@ -1907,16 +1907,13 @@ void dispc_set_trans_key(enum omap_channel ch,
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enum omap_dss_trans_key_type type,
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u32 trans_key)
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{
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const struct dispc_reg tr_reg[] = {
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DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
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enable_clocks(1);
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if (ch == OMAP_DSS_CHANNEL_LCD)
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REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
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else /* OMAP_DSS_CHANNEL_DIGIT */
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REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
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dispc_write_reg(tr_reg[ch], trans_key);
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dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
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enable_clocks(0);
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}
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@ -1924,9 +1921,6 @@ void dispc_get_trans_key(enum omap_channel ch,
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enum omap_dss_trans_key_type *type,
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u32 *trans_key)
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{
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const struct dispc_reg tr_reg[] = {
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DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
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enable_clocks(1);
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if (type) {
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if (ch == OMAP_DSS_CHANNEL_LCD)
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@ -1938,7 +1932,7 @@ void dispc_get_trans_key(enum omap_channel ch,
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}
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if (trans_key)
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*trans_key = dispc_read_reg(tr_reg[ch]);
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*trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
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enable_clocks(0);
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}
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@ -2119,8 +2113,8 @@ static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
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}
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enable_clocks(1);
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dispc_write_reg(DISPC_TIMING_H, timing_h);
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dispc_write_reg(DISPC_TIMING_V, timing_v);
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dispc_write_reg(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD), timing_h);
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dispc_write_reg(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD), timing_v);
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enable_clocks(0);
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}
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@ -2161,7 +2155,7 @@ static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
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BUG_ON(pck_div < 2);
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enable_clocks(1);
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dispc_write_reg(DISPC_DIVISOR,
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dispc_write_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD),
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FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
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enable_clocks(0);
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}
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@ -2169,7 +2163,7 @@ static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
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static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
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{
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u32 l;
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l = dispc_read_reg(DISPC_DIVISOR);
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l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
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*lck_div = FLD_GET(l, 23, 16);
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*pck_div = FLD_GET(l, 7, 0);
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}
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@ -2195,7 +2189,7 @@ unsigned long dispc_lclk_rate(void)
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unsigned long r;
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u32 l;
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l = dispc_read_reg(DISPC_DIVISOR);
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l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
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lcd = FLD_GET(l, 23, 16);
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@ -2210,7 +2204,7 @@ unsigned long dispc_pclk_rate(void)
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unsigned long r;
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u32 l;
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l = dispc_read_reg(DISPC_DIVISOR);
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l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
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lcd = FLD_GET(l, 23, 16);
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pcd = FLD_GET(l, 7, 0);
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@ -2297,19 +2291,19 @@ void dispc_dump_regs(struct seq_file *s)
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DUMPREG(DISPC_CONTROL);
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DUMPREG(DISPC_CONFIG);
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DUMPREG(DISPC_CAPABLE);
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DUMPREG(DISPC_DEFAULT_COLOR0);
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DUMPREG(DISPC_DEFAULT_COLOR1);
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DUMPREG(DISPC_TRANS_COLOR0);
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DUMPREG(DISPC_TRANS_COLOR1);
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DUMPREG(DISPC_DEFAULT_COLOR(0));
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DUMPREG(DISPC_DEFAULT_COLOR(1));
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DUMPREG(DISPC_TRANS_COLOR(0));
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DUMPREG(DISPC_TRANS_COLOR(1));
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DUMPREG(DISPC_LINE_STATUS);
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DUMPREG(DISPC_LINE_NUMBER);
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DUMPREG(DISPC_TIMING_H);
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DUMPREG(DISPC_TIMING_V);
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DUMPREG(DISPC_POL_FREQ);
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DUMPREG(DISPC_DIVISOR);
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DUMPREG(DISPC_TIMING_H(0));
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DUMPREG(DISPC_TIMING_V(0));
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DUMPREG(DISPC_POL_FREQ(0));
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DUMPREG(DISPC_DIVISOR(0));
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DUMPREG(DISPC_GLOBAL_ALPHA);
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DUMPREG(DISPC_SIZE_DIG);
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DUMPREG(DISPC_SIZE_LCD);
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DUMPREG(DISPC_SIZE_LCD(0));
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DUMPREG(DISPC_GFX_BA0);
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DUMPREG(DISPC_GFX_BA1);
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@ -2323,13 +2317,13 @@ void dispc_dump_regs(struct seq_file *s)
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DUMPREG(DISPC_GFX_WINDOW_SKIP);
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DUMPREG(DISPC_GFX_TABLE_BA);
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DUMPREG(DISPC_DATA_CYCLE1);
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DUMPREG(DISPC_DATA_CYCLE2);
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DUMPREG(DISPC_DATA_CYCLE3);
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DUMPREG(DISPC_DATA_CYCLE1(0));
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DUMPREG(DISPC_DATA_CYCLE2(0));
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DUMPREG(DISPC_DATA_CYCLE3(0));
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DUMPREG(DISPC_CPR_COEF_R);
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DUMPREG(DISPC_CPR_COEF_G);
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DUMPREG(DISPC_CPR_COEF_B);
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DUMPREG(DISPC_CPR_COEF_R(0));
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DUMPREG(DISPC_CPR_COEF_G(0));
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DUMPREG(DISPC_CPR_COEF_B(0));
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DUMPREG(DISPC_GFX_PRELOAD);
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@ -2446,7 +2440,7 @@ static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
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l |= FLD_VAL(acb, 7, 0);
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enable_clocks(1);
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dispc_write_reg(DISPC_POL_FREQ, l);
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dispc_write_reg(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD), l);
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enable_clocks(0);
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}
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@ -2537,8 +2531,8 @@ int dispc_get_clock_div(struct dispc_clock_info *cinfo)
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fck = dispc_fclk_rate();
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cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
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cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
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cinfo->lck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 23, 16);
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cinfo->pck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 7, 0);
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cinfo->lck = fck / cinfo->lck_div;
|
||||
cinfo->pck = cinfo->lck / cinfo->pck_div;
|
||||
|
|
Loading…
Reference in New Issue