mirror of https://gitee.com/openkylin/linux.git
iommu/mediatek: Modify MMU_CTRL register setting
The MMU_CTRL register of MT8173 is different from other SoCs. The in_order_wr_en is bit[9] which is zero by default. Other SoCs have the vitcim_tlb_en feature mapped to bit[12]. This bit is set to one by default. We need to preserve the bit when setting F_MMU_TF_PROT_TO_PROGRAM_ADDR as otherwise the bit will be cleared and IOMMU performance will drop. Signed-off-by: Chao Hao <chao.hao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Yong Wu <yong.wu@mediatek.com> Link: https://lore.kernel.org/r/20200703044127.27438-10-chao.hao@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -555,11 +555,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
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return ret;
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return ret;
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}
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}
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if (data->plat_data->m4u_plat == M4U_MT8173)
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if (data->plat_data->m4u_plat == M4U_MT8173) {
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regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
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regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
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F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
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F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
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else
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} else {
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regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR;
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regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
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regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
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}
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writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
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writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
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regval = F_L2_MULIT_HIT_EN |
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regval = F_L2_MULIT_HIT_EN |
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