mirror of https://gitee.com/openkylin/linux.git
Merge branch 'clps711x/cleanup' into next/cleanup
A single patch from Alexander Shiyan <shc_work@mail.ru>: * clps711x/cleanup: ARM: clps711x: Using a single definition for the PHYS and VIRT registers offset Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
86822f816f
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@ -23,16 +23,7 @@
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#ifndef __ASM_HARDWARE_CLPS7111_H
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#define __ASM_HARDWARE_CLPS7111_H
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#define CLPS7111_PHYS_BASE (0x80000000)
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#ifndef __ASSEMBLY__
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#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
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#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
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#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
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#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
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#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
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#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
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#endif
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#define CLPS711X_PHYS_BASE (0x80000000)
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#define PADR (0x0000)
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#define PBDR (0x0001)
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@ -23,15 +23,6 @@
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#ifndef __ASM_HARDWARE_EP7211_H
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#define __ASM_HARDWARE_EP7211_H
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#include <asm/hardware/clps7111.h>
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/*
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* define EP7211_BASE to be the base address of the region
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* you want to access.
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*/
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#define EP7211_PHYS_BASE (0x80000000)
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/*
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* XXX miket@bluemug.com: need to introduce EP7211 registers (those not
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* present in 7212) here.
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@ -23,18 +23,6 @@
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#ifndef __ASM_HARDWARE_EP7212_H
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#define __ASM_HARDWARE_EP7212_H
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/*
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* define EP7212_BASE to be the base address of the region
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* you want to access.
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*/
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#define EP7212_PHYS_BASE (0x80000000)
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#ifndef __ASSEMBLY__
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#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
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#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
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#endif
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/*
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* These registers are specific to the EP7212 only
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*/
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@ -36,7 +36,6 @@
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/clps7111.h>
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#include <asm/system_misc.h>
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/*
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@ -44,8 +43,8 @@
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*/
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static struct map_desc clps711x_io_desc[] __initdata = {
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{
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.virtual = CLPS7111_VIRT_BASE,
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.pfn = __phys_to_pfn(CLPS7111_PHYS_BASE),
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.virtual = (unsigned long)CLPS711X_VIRT_BASE,
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.pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
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.length = SZ_1M,
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.type = MT_DEVICE
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}
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@ -12,7 +12,6 @@
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/clps7111.h>
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.macro addruart, rp, rv, tmp
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#ifndef CONFIG_DEBUG_CLPS711X_UART2
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@ -20,8 +19,8 @@
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#else
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mov \rp, #0x1000 @ UART2
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#endif
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orr \rv, \rp, #CLPS7111_VIRT_BASE
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orr \rp, \rp, #CLPS7111_PHYS_BASE
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orr \rv, \rp, #CLPS711X_VIRT_BASE
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orr \rp, \rp, #CLPS711X_PHYS_BASE
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.endm
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.macro senduart,rd,rx
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@ -8,7 +8,6 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/clps7111.h>
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.macro get_irqnr_preamble, base, tmp
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.endm
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@ -18,7 +17,7 @@
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#endif
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.macro get_irqnr_and_base, irqnr, stat, base, mask
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mov \base, #CLPS7111_BASE
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mov \base, #CLPS711X_VIRT_BASE
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ldr \stat, [\base, #INTSR1]
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ldr \mask, [\base, #INTMR1]
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mov \irqnr, #4
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@ -19,12 +19,21 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#ifndef __MACH_HARDWARE_H
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#define __MACH_HARDWARE_H
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#include <asm/hardware/clps7111.h>
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#define CLPS7111_VIRT_BASE 0xff000000
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#define CLPS7111_BASE CLPS7111_VIRT_BASE
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#define CLPS711X_VIRT_BASE IOMEM(0xff000000)
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#ifndef __ASSEMBLY__
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#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off))
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#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off))
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#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off))
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#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off))
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#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off))
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#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off))
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#endif
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/*
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* The physical addresses that the external chip select signals map to is
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@ -54,14 +63,10 @@
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#if defined (CONFIG_ARCH_EP7211)
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#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
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#define EP7211_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/ep7211.h>
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#elif defined (CONFIG_ARCH_EP7212)
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#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
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#define EP7212_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/ep7212.h>
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#endif
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@ -71,10 +76,6 @@
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#if defined (CONFIG_ARCH_AUTCPU12)
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#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
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#define CS89712_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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#include <asm/hardware/cs89712.h>
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@ -83,15 +84,9 @@
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#if defined (CONFIG_ARCH_CDB89712)
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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#include <asm/hardware/cs89712.h>
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/* static cdb89712_map_io() areas */
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#define REGISTER_START 0x80000000
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#define REGISTER_SIZE 0x4000
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#define REGISTER_BASE 0xff000000
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#define ETHER_START 0x20000000
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#define ETHER_SIZE 0x1000
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#define ETHER_BASE 0xfe000000
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@ -154,13 +149,8 @@
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#if defined (CONFIG_ARCH_CEIVA)
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#define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
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#define CEIVA_BASE CLPS7111_VIRT_BASE
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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/*
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* The two flash banks are wired to chip selects 0 and 1. This is the mapping
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* for them.
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@ -18,7 +18,7 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/leds.h>
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#include <asm/hardware/clps7111.h>
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#include <mach/hardware.h>
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extern void clps711x_setup_timer(void);
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@ -17,15 +17,8 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/clps7111.h>
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#undef CLPS7111_BASE
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#define CLPS7111_BASE CLPS7111_PHYS_BASE
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#define __raw_readl(p) (*(unsigned long *)(p))
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#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
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#ifdef CONFIG_DEBUG_CLPS711X_UART2
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#define SYSFLGx SYSFLG2
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#define UARTDRx UARTDR2
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#define UARTDRx UARTDR1
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#endif
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#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x)))
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/*
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* The following code assumes the serial port has already been
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* initialized by the bootloader. If you didn't setup a port in
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* your bootloader then nothing will appear (which might be desired).
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*
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* This does not append a newline
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*/
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static inline void putc(int c)
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{
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while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
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while (phys_reg(SYSFLGx) & SYSFLG_UTXFF)
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barrier();
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clps_writel(c, UARTDRx);
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phys_reg(UARTDRx) = c;
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}
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static inline void flush(void)
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{
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while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
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while (phys_reg(SYSFLGx) & SYSFLG_UBUSY)
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barrier();
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}
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#include <asm/leds.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/clps7111.h>
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#include <asm/hardware/ep7212.h>
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static void p720t_leds_event(led_event_t ledevt)
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{
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unsigned long flags;
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@ -102,10 +102,10 @@ static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd,
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void __iomem *addr;
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unsigned char bits;
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addr = CS89712_VIRT_BASE + AUTCPU12_SMC_PORT_OFFSET;
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bits = (ctrl & NAND_CLE) << 4;
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bits = clps_readb(AUTCPU12_SMC_PORT_OFFSET) & ~0x30;
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bits |= (ctrl & NAND_CLE) << 4;
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bits |= (ctrl & NAND_ALE) << 2;
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writeb((readb(addr) & ~0x30) | bits, addr);
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clps_writeb(bits, AUTCPU12_SMC_PORT_OFFSET);
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addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
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writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
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*/
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int autcpu12_device_ready(struct mtd_info *mtd)
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{
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void __iomem *addr = CS89712_VIRT_BASE + AUTCPU12_SMC_PORT_OFFSET;
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return readb(addr) & AUTCPU12_SMC_RDY;
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return clps_readb(AUTCPU12_SMC_PORT_OFFSET) & AUTCPU12_SMC_RDY;
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}
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/*
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <mach/hardware.h> /* for CLPS7111_VIRT_BASE */
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#include <mach/hardware.h>
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#include <asm/sizes.h>
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#include <mach/h1900-gpio.h>
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#include <mach/ipaq.h>
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@ -40,7 +40,6 @@
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/hardware/clps7111.h>
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#define UART_NR 2
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@ -33,7 +33,6 @@
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#include <asm/mach-types.h>
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#include <linux/uaccess.h>
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#include <asm/hardware/clps7111.h>
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#include <mach/syspld.h>
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struct fb_info *cfb;
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