mirror of https://gitee.com/openkylin/linux.git
Qualcomm ARM Based Device Tree Updates for v3.15
* Added device tree nodes to enable SMP on msm8660, msm8960, and msm8974 * Added Random Number Generator DT nodes for msm8974 and msm8960 SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJTBjOdAAoJEF9hYXeAcXzBk08P/iOLKjmyRtNoR2A34X3TXLam 665yyGi6MEa9Kj0AugMgsZld33Nc90z0g4PjujBDEjAA8PzwuQ/9+hYngznRy3+6 by+lNUO9IUlHZm/XDjEP+iGbKjFnr3wCwHgsqi/r1IxgaZJO8uRGhsUWmkeLRMeS PfIKeVemBLKibmfuGee+dRDWL91yfWTbV0SphIQ0gY9CTPDhvg+hZVdSqthTsYat UdsXqII2D2HsuJS9XPe4ZHY+fvYnIY8GOfvwIN1vy0y+BUfEQDl4b9WgwE6SQlIf E1P//udmjsk+gIXJjKTCJzHgdSj0EQZ0KKGf1oD+XZQ2pdMxfK726EJT3Ih3J+og gbhidyTq3H7fn5LDlicHB4MpcJuph8o7W8SvAUqhlU0aRklS+ck3XOCM5wUilbGC pFB4dbFIHulYRkdTa0SNmxOKQsz8GvikOZs3vDcpR9Z9qgB5w2LYcPxkG4EzZXD7 1I/zrb4e/hyNPoFU88RF1AistXa4g7x6gaH6oD7MJd2TLydQlAC6Yd3JHI7h4z7i o73X32IDk8NweKVIwKQnrKXdxhCKztYLxDzuyB9+p5kyzKBl1/M4suetl8DkTo0b Ebr6tXZBTcvcSbKxF8SZdsJwGOiimMu8AGMv3tpNNGV9Cj/QWHZX2wnHuwaJcgKV njij2D60uOCHu0LhNOSq =4u6J -----END PGP SIGNATURE----- Merge tag 'qcom-dt-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt Merge "Qualcomm ARM Based Device Tree Updates for v3.15" from Kumar Gala * Added device tree nodes to enable SMP on msm8660, msm8960, and msm8974 * Added Random Number Generator DT nodes for msm8974 and msm8960 SoCs * tag 'qcom-dt-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: dts: qcom-msm8960-cdp: Add RNG device tree node ARM: dts: qcom: Add RNG device tree node ARM: dts: qcom: Add nodes necessary for SMP boot Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
86a37e52bb
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@ -9,6 +9,30 @@ / {
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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@ -9,6 +9,36 @@ / {
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compatible = "qcom,msm8960";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <1 14 0x304>;
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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interrupts = <0 2 0x4>;
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};
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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@ -53,6 +83,28 @@ clock-controller@4000000 {
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#reset-cells = <1>;
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: regulator@2099000 {
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compatible = "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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serial@16440000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16440000 0x1000>,
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@ -67,4 +119,11 @@ qcom,ssbi@500000 {
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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rng@1a500000 {
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compatible = "qcom,prng";
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reg = <0x1a500000 0x200>;
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clocks = <&gcc PRNG_CLK>;
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clock-names = "core";
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};
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};
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@ -9,6 +9,49 @@ / {
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compatible = "qcom,msm8974";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <1 9 0xf04>;
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v2";
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc2>;
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};
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cpu@3 {
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc3>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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interrupts = <0 2 0x4>;
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qcom,saw = <&saw_l2>;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -91,6 +134,32 @@ frame@f9028000 {
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};
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};
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saw_l2: regulator@f9012000 {
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compatible = "qcom,saw2";
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reg = <0xf9012000 0x1000>;
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regulator;
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};
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acc0: clock-controller@f9088000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
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};
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acc1: clock-controller@f9098000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
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};
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acc2: clock-controller@f90a8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
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};
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acc3: clock-controller@f90b8000 {
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compatible = "qcom,kpss-acc-v2";
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reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
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};
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restart@fc4ab000 {
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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@ -117,5 +186,12 @@ serial@f991e000 {
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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};
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rng@f9bff000 {
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compatible = "qcom,prng";
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reg = <0xf9bff000 0x200>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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};
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};
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