mirror of https://gitee.com/openkylin/linux.git
Merge branch 'remotes/lorenzo/pci/dt'
- Add common schema for PCI endpoint controllers (Kishon Vijay Abraham I)
- Add host and endpoint schemas for Cadence PCIe core (Kishon Vijay
Abraham I)
- Convert Cadence platform bindings to DT schema (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/dt:
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema
dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
dt-bindings: PCI: Add PCI Endpoint Controller Schema
This commit is contained in:
Bjorn Helgaas
commit
86d0b6a131
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@ -1,27 +0,0 @@
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* Cadence PCIe endpoint controller
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Required properties:
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- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
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- reg: Should contain the controller register base address and AXI interface
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region base address respectively.
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- reg-names: Must be "reg" and "mem" respectively.
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- cdns,max-outbound-regions: Set to maximum number of outbound regions
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Optional properties:
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- max-functions: Maximum number of functions that can be configured (default 1).
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- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
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than one in the list. If only one PHY listed it must manage all lanes.
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- phy-names: List of names to identify the PHY.
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Example:
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pcie@fc000000 {
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compatible = "cdns,cdns-pcie-ep";
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reg = <0x0 0xfc000000 0x0 0x01000000>,
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<0x0 0x80000000 0x0 0x40000000>;
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reg-names = "reg", "mem";
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cdns,max-outbound-regions = <16>;
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max-functions = /bits/ 8 <8>;
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phys = <&ep_phy0 &ep_phy1>;
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phy-names = "pcie-lane0","pcie-lane1";
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};
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@ -0,0 +1,49 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence PCIe EP Controller
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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allOf:
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- $ref: "cdns-pcie.yaml#"
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- $ref: "pci-ep.yaml#"
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properties:
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compatible:
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const: cdns,cdns-pcie-ep
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: reg
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- const: mem
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required:
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- reg
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- reg-names
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie-ep@fc000000 {
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compatible = "cdns,cdns-pcie-ep";
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reg = <0x0 0xfc000000 0x0 0x01000000>,
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<0x0 0x80000000 0x0 0x40000000>;
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reg-names = "reg", "mem";
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cdns,max-outbound-regions = <16>;
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max-functions = /bits/ 8 <8>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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};
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};
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...
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@ -1,66 +0,0 @@
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* Cadence PCIe host controller
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This PCIe controller inherits the base properties defined in
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host-generic-pci.txt.
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Required properties:
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- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
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- reg: Should contain the controller register base address, PCIe configuration
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window base address, and AXI interface region base address respectively.
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- reg-names: Must be "reg", "cfg" and "mem" respectively.
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- #address-cells: Set to <3>
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- #size-cells: Set to <2>
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- device_type: Set to "pci"
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- ranges: Ranges for the PCI memory and I/O regions
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- #interrupt-cells: Set to <1>
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- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- cdns,max-outbound-regions: Set to maximum number of outbound regions
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(default 32)
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- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
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number of least significant bits kept during inbound (PCIe -> AXI) address
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translations (default 32)
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- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
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- device-id: The PCI device ID (16 bits, default is design dependent)
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- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
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than one in the list. If only one PHY listed it must manage all lanes.
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- phy-names: List of names to identify the PHY.
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Example:
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pcie@fb000000 {
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compatible = "cdns,cdns-pcie-host";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xff>;
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linux,pci-domain = <0>;
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cdns,max-outbound-regions = <16>;
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cdns,no-bar-match-nbits = <32>;
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vendor-id = /bits/ 16 <0x17cd>;
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device-id = /bits/ 16 <0x0200>;
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reg = <0x0 0xfb000000 0x0 0x01000000>,
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<0x0 0x41000000 0x0 0x00001000>,
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<0x0 0x40000000 0x0 0x04000000>;
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reg-names = "reg", "cfg", "mem";
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ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
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<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
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#interrupt-cells = <0x1>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1
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0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1
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0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1
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0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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msi-parent = <&its_pci>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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};
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@ -0,0 +1,76 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence PCIe host controller
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- $ref: "cdns-pcie-host.yaml#"
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properties:
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compatible:
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const: cdns,cdns-pcie-host
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: reg
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- const: cfg
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- const: mem
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msi-parent: true
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required:
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- reg
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- reg-names
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@fb000000 {
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compatible = "cdns,cdns-pcie-host";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xff>;
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linux,pci-domain = <0>;
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cdns,max-outbound-regions = <16>;
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cdns,no-bar-match-nbits = <32>;
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vendor-id = <0x17cd>;
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device-id = <0x0200>;
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reg = <0x0 0xfb000000 0x0 0x01000000>,
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<0x0 0x41000000 0x0 0x00001000>,
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<0x0 0x40000000 0x0 0x04000000>;
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reg-names = "reg", "cfg", "mem";
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ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
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<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
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#interrupt-cells = <0x1>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>,
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<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>,
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<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>,
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<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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msi-parent = <&its_pci>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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};
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};
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...
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@ -0,0 +1,27 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Cadence PCIe Host
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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allOf:
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- $ref: "/schemas/pci/pci-bus.yaml#"
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- $ref: "cdns-pcie.yaml#"
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properties:
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cdns,no-bar-match-nbits:
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description:
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Set into the no BAR match register to configure the number of least
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significant bits kept during inbound (PCIe -> AXI) address translations
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 64
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default: 32
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msi-parent: true
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@ -0,0 +1,31 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Cadence PCIe Core
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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properties:
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cdns,max-outbound-regions:
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description: maximum number of outbound regions
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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default: 32
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phys:
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description:
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One per lane if more than one in the list. If only one PHY listed it must
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manage all lanes.
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minItems: 1
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maxItems: 16
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phy-names:
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items:
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- const: pcie-phy
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# FIXME: names when more than 1
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@ -0,0 +1,41 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/pci-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PCI Endpoint Controller Schema
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description: |
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Common properties for PCI Endpoint Controller Nodes.
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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properties:
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$nodename:
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pattern: "^pcie-ep@"
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max-functions:
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description: Maximum number of functions that can be configured
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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default: 1
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maximum: 255
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max-link-speed:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 1, 2, 3, 4 ]
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num-lanes:
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description: maximum number of lanes
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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default: 1
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maximum: 16
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required:
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- compatible
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@ -12739,7 +12739,7 @@ PCI DRIVER FOR CADENCE PCIE IP
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M: Tom Joseph <tjoseph@cadence.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/cdns,*.txt
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F: Documentation/devicetree/bindings/pci/cdns,*
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F: drivers/pci/controller/pcie-cadence*
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PCI DRIVER FOR FREESCALE LAYERSCAPE
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|
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