From 8703ba77ec555b08c538beb728a4df1b72e0213e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 29 Jul 2019 10:03:56 +0200 Subject: [PATCH] arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of August 24, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) and D3 (r8a77995). * TX clock internal delay mode is required for reliable 1Gbps communication using the KSZ9031RNX phy present on the Ebisu and Draak boards. Thus, the E3 based Ebisu and D3 based Draak boards can not reliably use 1Gbps and the speed should be limited to 100Mbps. Based on work by Kazuya Mizuguchi. Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang Reviewed-by: Andrew Lunn Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 81db803f4389..b38f9d442fc0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -271,6 +271,14 @@ phy0: ethernet-phy@0 { interrupt-parent = <&gpio2>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + /* + * TX clock internal delay mode is required for reliable + * 1Gbps communication using the KSZ9031RNX phy present on + * the Ebisu board, however, TX clock internal delay mode + * isn't supported on r8a77990. Thus, limit speed to + * 100Mbps for reliable communication. + */ + max-speed = <100>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index fe14792cedfb..0bbd4d701042 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -175,6 +175,14 @@ phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&gpio5>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + /* + * TX clock internal delay mode is required for reliable + * 1Gbps communication using the KSZ9031RNX phy present on + * the Draak board, however, TX clock internal delay mode + * isn't supported on r8a77995. Thus, limit speed to + * 100Mbps for reliable communication. + */ + max-speed = <100>; }; };