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ARM: dts: artpec: add disabled node for PCIe endpoint mode 

The PCIe controller in the artpec6 SoC supports both root complex and
endpoint mode, however, the controller can only be used in one of the
modes.

Both pci nodes are disabled by default. A DTS file can enable one of
them, depending on what mode it wants to run.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Niklas Cassel 2018-02-21 09:59:59 +01:00 committed by Arnd Bergmann
parent e4202ef7b9
commit 870e0ecc31
1 changed files with 18 additions and 0 deletions
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18
arch/arm/boot/dts/artpec6.dtsi
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@ -154,6 +154,10 @@ pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};
/*
* Both pci nodes cannot be enabled at the same time,
* leave the unwanted node as disabled.
*/
pcie: pcie@f8050000 {
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
reg = <0xf8050000 0x2000
@ -181,6 +185,20 @@ pcie: pcie@f8050000 {
status = "disabled";
};
pcie_ep: pcie_ep@f8050000 {
compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
reg = <0xf8050000 0x2000
0xf8051000 0x2000
0xf8040000 0x1000
0xc0000000 0x20000000>;
reg-names = "dbi", "dbi2", "phy", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <2>;
num-lanes = <2>;
axis,syscon-pcie = <&syscon>;
status = "disabled";
};
pinctrl: pinctrl@f801d000 {
compatible = "axis,artpec6-pinctrl";
reg = <0xf801d000 0x400>;