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drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk. 

[Description]
DMUB is using DPREF CLK, but DMCU still use displayclk.
This is for updating DMCU wait_for_loop after display clock change.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2019-05-09 13:04:07 -04:00 committed by Alex Deucher
parent 45021f8ea5
commit 8712bda45c
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
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@ -175,6 +175,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
bool update_dispclk = false;
bool enter_display_off = false;
bool dpp_clock_lowered = false;
struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
display_count = get_active_display_cnt(dc, context);
if (dc->res_pool->pp_smu)
@ -357,6 +358,7 @@ void dcn20_clk_mgr_construct(
* this works because the int part is on the right edge of the register
* and the frac part is on the left edge
*/
pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;