mirror of https://gitee.com/openkylin/linux.git
Merge branches 'clk-qcom-rpmh', 'clk-npcm7xx', 'clk-of-parent-count' and 'clk-qcom-rcg-fix' into clk-next
* clk-qcom-rpmh: dt-bindings: clock: Introduce QCOM RPMh clock bindings * clk-npcm7xx: clk: npcm7xx: fix return value check in npcm7xx_clk_init() clk: npcm7xx: add clock controller dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock * clk-of-parent-count: pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding clk: Extract OF clock helpers in <linux/of_clk.h> * clk-qcom-rcg-fix: clk: qcom: Base rcg parent rate off plan frequency
This commit is contained in:
Stephen Boyd
commit
872e47f75f
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@ -0,0 +1,100 @@
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* Nuvoton NPCM7XX Clock Controller
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Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
|
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generates and supplies clocks to all modules within the BMC.
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External clocks:
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|
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There are six fixed clocks that are generated outside the BMC. All clocks are of
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a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
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clk_sysbypck are inputs to the clock controller.
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clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
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network. They are set on the device tree, but not used by the clock module. The
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network devices use them directly.
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Example can be found below.
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|
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All available clocks are defined as preprocessor macros in:
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dt-bindings/clock/nuvoton,npcm7xx-clock.h
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and can be reused as DT sources.
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Required Properties of clock controller:
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- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
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Poleg BMC NPCM750
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- reg: physical base address of the clock controller and length of
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memory mapped region.
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- #clock-cells: should be 1.
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Example: Clock controller node:
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clk: clock-controller@f0801000 {
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compatible = "nuvoton,npcm750-clk";
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#clock-cells = <1>;
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reg = <0xf0801000 0x1000>;
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clock-names = "refclk", "sysbypck", "mcbypck";
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clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
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};
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Example: Required external clocks for network:
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/* external reference clock */
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clk_refclk: clk-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "refclk";
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};
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/* external reference clock for cpu. float in normal operation */
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clk_sysbypck: clk-sysbypck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "sysbypck";
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};
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/* external reference clock for MC. float in normal operation */
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clk_mcbypck: clk-mcbypck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <800000000>;
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clock-output-names = "mcbypck";
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};
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/* external clock signal rg1refck, supplied by the phy */
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clk_rg1refck: clk-rg1refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk_rg1refck";
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};
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/* external clock signal rg2refck, supplied by the phy */
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clk_rg2refck: clk-rg2refck {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "clk_rg2refck";
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};
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clk_xin: clk-xin {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "clk_xin";
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};
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Example: GMAC controller node that consumes two clocks: a generated clk by the
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clock controller and a fixed clock from DT (clk_rg1refck).
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ethernet0: ethernet@f0802000 {
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compatible = "snps,dwmac";
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reg = <0xf0802000 0x2000>;
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interrupts = <0 14 4>;
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interrupt-names = "macirq";
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clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
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clock-names = "stmmaceth", "clk_gmac";
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};
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@ -0,0 +1,22 @@
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Qualcomm Technologies, Inc. RPMh Clocks
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-------------------------------------------------------
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Resource Power Manager Hardened (RPMh) manages shared resources on
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some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
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other hardware subsystems via RSC to control clocks.
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Required properties :
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- compatible : shall contain "qcom,sdm845-rpmh-clk"
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- #clock-cells : must contain 1
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Example :
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#include <dt-bindings/clock/qcom,rpmh.h>
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&apps_rsc {
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rpmhcc: clock-controller {
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compatible = "qcom,sdm845-rpmh-clk";
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#clock-cells = <1>;
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};
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};
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@ -3556,6 +3556,7 @@ F: drivers/clk/
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X: drivers/clk/clkdev.c
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F: include/linux/clk-pr*
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F: include/linux/clk/
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F: include/linux/of_clk.h
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COMMON INTERNET FILE SYSTEM (CIFS)
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M: Steve French <sfrench@samba.org>
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|
|
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@ -33,6 +33,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
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obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
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obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
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obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
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obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
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obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
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obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
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@ -0,0 +1,656 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Nuvoton NPCM7xx Clock Generator
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* All the clocks are initialized by the bootloader, so this driver allow only
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* reading of current settings directly from the hardware.
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*
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* Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
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*/
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/bitfield.h>
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#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
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struct npcm7xx_clk_pll {
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struct clk_hw hw;
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void __iomem *pllcon;
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u8 flags;
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};
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#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
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#define PLLCON_LOKI BIT(31)
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#define PLLCON_LOKS BIT(30)
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#define PLLCON_FBDV GENMASK(27, 16)
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#define PLLCON_OTDV2 GENMASK(15, 13)
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#define PLLCON_PWDEN BIT(12)
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#define PLLCON_OTDV1 GENMASK(10, 8)
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#define PLLCON_INDV GENMASK(5, 0)
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static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
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unsigned long fbdv, indv, otdv1, otdv2;
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unsigned int val;
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u64 ret;
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if (parent_rate == 0) {
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pr_err("%s: parent rate is zero", __func__);
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return 0;
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}
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val = readl_relaxed(pll->pllcon);
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indv = FIELD_GET(PLLCON_INDV, val);
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fbdv = FIELD_GET(PLLCON_FBDV, val);
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otdv1 = FIELD_GET(PLLCON_OTDV1, val);
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otdv2 = FIELD_GET(PLLCON_OTDV2, val);
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ret = (u64)parent_rate * fbdv;
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do_div(ret, indv * otdv1 * otdv2);
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return ret;
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}
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static const struct clk_ops npcm7xx_clk_pll_ops = {
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.recalc_rate = npcm7xx_clk_pll_recalc_rate,
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};
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static struct clk_hw *
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npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
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const char *parent_name, unsigned long flags)
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{
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struct npcm7xx_clk_pll *pll;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
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init.name = name;
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init.ops = &npcm7xx_clk_pll_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = flags;
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pll->pllcon = pllcon;
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pll->hw.init = &init;
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hw = &pll->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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#define NPCM7XX_CLKEN1 (0x00)
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#define NPCM7XX_CLKEN2 (0x28)
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#define NPCM7XX_CLKEN3 (0x30)
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#define NPCM7XX_CLKSEL (0x04)
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#define NPCM7XX_CLKDIV1 (0x08)
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#define NPCM7XX_CLKDIV2 (0x2C)
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#define NPCM7XX_CLKDIV3 (0x58)
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#define NPCM7XX_PLLCON0 (0x0C)
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#define NPCM7XX_PLLCON1 (0x10)
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#define NPCM7XX_PLLCON2 (0x54)
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#define NPCM7XX_SWRSTR (0x14)
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#define NPCM7XX_IRQWAKECON (0x18)
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#define NPCM7XX_IRQWAKEFLAG (0x1C)
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#define NPCM7XX_IPSRST1 (0x20)
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#define NPCM7XX_IPSRST2 (0x24)
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#define NPCM7XX_IPSRST3 (0x34)
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#define NPCM7XX_WD0RCR (0x38)
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#define NPCM7XX_WD1RCR (0x3C)
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#define NPCM7XX_WD2RCR (0x40)
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#define NPCM7XX_SWRSTC1 (0x44)
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#define NPCM7XX_SWRSTC2 (0x48)
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#define NPCM7XX_SWRSTC3 (0x4C)
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#define NPCM7XX_SWRSTC4 (0x50)
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#define NPCM7XX_CORSTC (0x5C)
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#define NPCM7XX_PLLCONG (0x60)
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#define NPCM7XX_AHBCKFI (0x64)
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#define NPCM7XX_SECCNT (0x68)
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#define NPCM7XX_CNTR25M (0x6C)
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struct npcm7xx_clk_gate_data {
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u32 reg;
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u8 bit_idx;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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/*
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* If this clock is exported via DT, set onecell_idx to constant
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
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* this specific clock. Otherwise, set to -1.
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*/
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int onecell_idx;
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};
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struct npcm7xx_clk_mux_data {
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u8 shift;
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u8 mask;
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u32 *table;
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const char *name;
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const char * const *parent_names;
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u8 num_parents;
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unsigned long flags;
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/*
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* If this clock is exported via DT, set onecell_idx to constant
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* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
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* this specific clock. Otherwise, set to -1.
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*/
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int onecell_idx;
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|
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};
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struct npcm7xx_clk_div_fixed_data {
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u8 mult;
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u8 div;
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const char *name;
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const char *parent_name;
|
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u8 clk_divider_flags;
|
||||
/*
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||||
* If this clock is exported via DT, set onecell_idx to constant
|
||||
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
|
||||
* this specific clock. Otherwise, set to -1.
|
||||
*/
|
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int onecell_idx;
|
||||
};
|
||||
|
||||
|
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struct npcm7xx_clk_div_data {
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u32 reg;
|
||||
u8 shift;
|
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u8 width;
|
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const char *name;
|
||||
const char *parent_name;
|
||||
u8 clk_divider_flags;
|
||||
unsigned long flags;
|
||||
/*
|
||||
* If this clock is exported via DT, set onecell_idx to constant
|
||||
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
|
||||
* this specific clock. Otherwise, set to -1.
|
||||
*/
|
||||
int onecell_idx;
|
||||
};
|
||||
|
||||
struct npcm7xx_clk_pll_data {
|
||||
u32 reg;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
/*
|
||||
* If this clock is exported via DT, set onecell_idx to constant
|
||||
* defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
|
||||
* this specific clock. Otherwise, set to -1.
|
||||
*/
|
||||
int onecell_idx;
|
||||
};
|
||||
|
||||
/*
|
||||
* Single copy of strings used to refer to clocks within this driver indexed by
|
||||
* above enum.
|
||||
*/
|
||||
#define NPCM7XX_CLK_S_REFCLK "refclk"
|
||||
#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck"
|
||||
#define NPCM7XX_CLK_S_MCBYPCK "mcbypck"
|
||||
#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck"
|
||||
#define NPCM7XX_CLK_S_PLL0 "pll0"
|
||||
#define NPCM7XX_CLK_S_PLL1 "pll1"
|
||||
#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2"
|
||||
#define NPCM7XX_CLK_S_PLL2 "pll2"
|
||||
#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx"
|
||||
#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2"
|
||||
#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel"
|
||||
#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
|
||||
#define NPCM7XX_CLK_S_MC_MUX "mc_phy"
|
||||
#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/
|
||||
#define NPCM7XX_CLK_S_MC "mc"
|
||||
#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/
|
||||
#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/
|
||||
#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux"
|
||||
#define NPCM7XX_CLK_S_UART_MUX "uart_mux"
|
||||
#define NPCM7XX_CLK_S_TIM_MUX "timer_mux"
|
||||
#define NPCM7XX_CLK_S_SD_MUX "sd_mux"
|
||||
#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux"
|
||||
#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux"
|
||||
#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux"
|
||||
#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux"
|
||||
#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel"
|
||||
#define NPCM7XX_CLK_S_SPI0 "spi0"
|
||||
#define NPCM7XX_CLK_S_SPI3 "spi3"
|
||||
#define NPCM7XX_CLK_S_SPIX "spix"
|
||||
#define NPCM7XX_CLK_S_APB1 "apb1"
|
||||
#define NPCM7XX_CLK_S_APB2 "apb2"
|
||||
#define NPCM7XX_CLK_S_APB3 "apb3"
|
||||
#define NPCM7XX_CLK_S_APB4 "apb4"
|
||||
#define NPCM7XX_CLK_S_APB5 "apb5"
|
||||
#define NPCM7XX_CLK_S_TOCK "tock"
|
||||
#define NPCM7XX_CLK_S_CLKOUT "clkout"
|
||||
#define NPCM7XX_CLK_S_UART "uart"
|
||||
#define NPCM7XX_CLK_S_TIMER "timer"
|
||||
#define NPCM7XX_CLK_S_MMC "mmc"
|
||||
#define NPCM7XX_CLK_S_SDHC "sdhc"
|
||||
#define NPCM7XX_CLK_S_ADC "adc"
|
||||
#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem"
|
||||
#define NPCM7XX_CLK_S_USBIF "serial_usbif"
|
||||
#define NPCM7XX_CLK_S_USB_HOST "usb_host"
|
||||
#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge"
|
||||
#define NPCM7XX_CLK_S_PCI "pci"
|
||||
|
||||
static u32 pll_mux_table[] = {0, 1, 2, 3};
|
||||
static const char * const pll_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_PLL0,
|
||||
NPCM7XX_CLK_S_PLL1_DIV2,
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_PLL2_DIV2,
|
||||
};
|
||||
|
||||
static u32 cpuck_mux_table[] = {0, 1, 2, 3};
|
||||
static const char * const cpuck_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_PLL0,
|
||||
NPCM7XX_CLK_S_PLL1_DIV2,
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_SYSBYPCK,
|
||||
};
|
||||
|
||||
static u32 pixcksel_mux_table[] = {0, 2};
|
||||
static const char * const pixcksel_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_PLL_GFX,
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
};
|
||||
|
||||
static u32 sucksel_mux_table[] = {2, 3};
|
||||
static const char * const sucksel_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_PLL2_DIV2,
|
||||
};
|
||||
|
||||
static u32 mccksel_mux_table[] = {0, 2, 3};
|
||||
static const char * const mccksel_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_PLL1_DIV2,
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_MCBYPCK,
|
||||
};
|
||||
|
||||
static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
|
||||
static const char * const clkoutsel_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_PLL0,
|
||||
NPCM7XX_CLK_S_PLL1_DIV2,
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_PLL_GFX, // divided by 2
|
||||
NPCM7XX_CLK_S_PLL2_DIV2,
|
||||
};
|
||||
|
||||
static u32 gfxmsel_mux_table[] = {2, 3};
|
||||
static const char * const gfxmsel_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_PLL2_DIV2,
|
||||
};
|
||||
|
||||
static u32 dvcssel_mux_table[] = {2, 3};
|
||||
static const char * const dvcssel_mux_parents[] __initconst = {
|
||||
NPCM7XX_CLK_S_REFCLK,
|
||||
NPCM7XX_CLK_S_PLL2,
|
||||
};
|
||||
|
||||
static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
|
||||
{NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
|
||||
|
||||
{NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
|
||||
NPCM7XX_CLK_S_REFCLK, 0, -1},
|
||||
|
||||
{NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
|
||||
NPCM7XX_CLK_S_REFCLK, 0, -1},
|
||||
|
||||
{NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
|
||||
NPCM7XX_CLK_S_REFCLK, 0, -1},
|
||||
};
|
||||
|
||||
static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
|
||||
{0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
|
||||
cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
|
||||
NPCM7XX_CLK_CPU},
|
||||
|
||||
{4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
|
||||
pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
|
||||
NPCM7XX_CLK_GFX_PIXEL},
|
||||
|
||||
{6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
|
||||
pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
|
||||
|
||||
{8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
|
||||
pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
|
||||
|
||||
{10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
|
||||
sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
|
||||
|
||||
{12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
|
||||
mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
|
||||
|
||||
{14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
|
||||
pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
|
||||
|
||||
{16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
|
||||
pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
|
||||
|
||||
{18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
|
||||
clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
|
||||
|
||||
{21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
|
||||
gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
|
||||
|
||||
{23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
|
||||
dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
|
||||
};
|
||||
|
||||
/* fixed ratio dividers (no register): */
|
||||
static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = {
|
||||
{ 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC},
|
||||
{ 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1},
|
||||
{ 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1},
|
||||
};
|
||||
|
||||
/* configurable dividers: */
|
||||
static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
|
||||
{NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
|
||||
NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
|
||||
/*30-28 ADCCKDIV*/
|
||||
{NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
|
||||
NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
|
||||
/*27-26 CLK4DIV*/
|
||||
{NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
|
||||
NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
|
||||
/*25-21 TIMCKDIV*/
|
||||
{NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
|
||||
NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
|
||||
/*20-16 UARTDIV*/
|
||||
{NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
|
||||
NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
|
||||
/*15-11 MMCCKDIV*/
|
||||
{NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
|
||||
NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
|
||||
/*10-6 AHB3CKDIV*/
|
||||
{NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
|
||||
NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
|
||||
/*5-2 PCICKDIV*/
|
||||
{NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
|
||||
NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
|
||||
NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
|
||||
|
||||
{NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
|
||||
NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
|
||||
/*31-30 APB4CKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
|
||||
NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
|
||||
/*29-28 APB3CKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
|
||||
NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
|
||||
/*27-26 APB2CKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
|
||||
NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
|
||||
/*25-24 APB1CKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
|
||||
NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
|
||||
/*23-22 APB5CKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
|
||||
NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
|
||||
/*20-16 CLKOUTDIV*/
|
||||
{NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
|
||||
NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
|
||||
/*15-13 GFXCKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
|
||||
NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
|
||||
/*12-8 SUCKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
|
||||
NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
|
||||
/*7-4 SU48CKDIV*/
|
||||
{NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
|
||||
NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
|
||||
,/*3-0 SD1CKDIV*/
|
||||
|
||||
{NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
|
||||
NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
|
||||
/*10-6 SPI0CKDV*/
|
||||
{NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
|
||||
NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
|
||||
/*5-1 SPIXCKDV*/
|
||||
|
||||
};
|
||||
|
||||
static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = {
|
||||
{NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0},
|
||||
{NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0},
|
||||
{NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0},
|
||||
{NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0},
|
||||
{NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0},
|
||||
{NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
/* bit 3 is reserved */
|
||||
{NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
|
||||
{NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0},
|
||||
/* bit 29 is reserved */
|
||||
{NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0},
|
||||
{NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
/* bit 24 is reserved */
|
||||
{NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0},
|
||||
{NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0},
|
||||
{NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
/* bit 20 is reserved */
|
||||
{NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0},
|
||||
{NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0},
|
||||
/* bit 17 is reserved */
|
||||
{NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
/* bit 15 is reserved */
|
||||
{NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
{NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0},
|
||||
|
||||
{NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0},
|
||||
{NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
/* bit 11 is reserved */
|
||||
/* bit 10 is reserved */
|
||||
{NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
/* bit 8 is reserved */
|
||||
{NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0},
|
||||
{NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0},
|
||||
{NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0},
|
||||
};
|
||||
|
||||
static DEFINE_SPINLOCK(npcm7xx_clk_lock);
|
||||
|
||||
static void __init npcm7xx_clk_init(struct device_node *clk_np)
|
||||
{
|
||||
struct clk_hw_onecell_data *npcm7xx_clk_data;
|
||||
void __iomem *clk_base;
|
||||
struct resource res;
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
ret = of_address_to_resource(clk_np, 0, &res);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to get resource, ret %d\n", clk_np->name,
|
||||
ret);
|
||||
return;
|
||||
}
|
||||
|
||||
clk_base = ioremap(res.start, resource_size(&res));
|
||||
if (!clk_base)
|
||||
goto npcm7xx_init_error;
|
||||
|
||||
npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) *
|
||||
NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL);
|
||||
if (!npcm7xx_clk_data)
|
||||
goto npcm7xx_init_np_err;
|
||||
|
||||
npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
|
||||
|
||||
for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
|
||||
npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
/* Register plls */
|
||||
for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
|
||||
const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
|
||||
|
||||
hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
|
||||
pll_data->name, pll_data->parent_name, pll_data->flags);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("npcm7xx_clk: Can't register pll\n");
|
||||
goto npcm7xx_init_fail;
|
||||
}
|
||||
|
||||
if (pll_data->onecell_idx >= 0)
|
||||
npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
|
||||
}
|
||||
|
||||
/* Register fixed dividers */
|
||||
hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
|
||||
NPCM7XX_CLK_S_PLL1, 0, 1, 2);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("npcm7xx_clk: Can't register fixed div\n");
|
||||
goto npcm7xx_init_fail;
|
||||
}
|
||||
|
||||
hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
|
||||
NPCM7XX_CLK_S_PLL2, 0, 1, 2);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("npcm7xx_clk: Can't register div2\n");
|
||||
goto npcm7xx_init_fail;
|
||||
}
|
||||
|
||||
/* Register muxes */
|
||||
for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
|
||||
const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
|
||||
|
||||
hw = clk_hw_register_mux_table(NULL,
|
||||
mux_data->name,
|
||||
mux_data->parent_names, mux_data->num_parents,
|
||||
mux_data->flags, clk_base + NPCM7XX_CLKSEL,
|
||||
mux_data->shift, mux_data->mask, 0,
|
||||
mux_data->table, &npcm7xx_clk_lock);
|
||||
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("npcm7xx_clk: Can't register mux\n");
|
||||
goto npcm7xx_init_fail;
|
||||
}
|
||||
|
||||
if (mux_data->onecell_idx >= 0)
|
||||
npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
|
||||
}
|
||||
|
||||
/* Register clock dividers specified in npcm7xx_divs */
|
||||
for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
|
||||
const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
|
||||
|
||||
hw = clk_hw_register_divider(NULL, div_data->name,
|
||||
div_data->parent_name,
|
||||
div_data->flags,
|
||||
clk_base + div_data->reg,
|
||||
div_data->shift, div_data->width,
|
||||
div_data->clk_divider_flags, &npcm7xx_clk_lock);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("npcm7xx_clk: Can't register div table\n");
|
||||
goto npcm7xx_init_fail;
|
||||
}
|
||||
|
||||
if (div_data->onecell_idx >= 0)
|
||||
npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
|
||||
}
|
||||
|
||||
ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
|
||||
npcm7xx_clk_data);
|
||||
if (ret)
|
||||
pr_err("failed to add DT provider: %d\n", ret);
|
||||
|
||||
of_node_put(clk_np);
|
||||
|
||||
return;
|
||||
|
||||
npcm7xx_init_fail:
|
||||
kfree(npcm7xx_clk_data->hws);
|
||||
npcm7xx_init_np_err:
|
||||
iounmap(clk_base);
|
||||
npcm7xx_init_error:
|
||||
of_node_put(clk_np);
|
||||
}
|
||||
CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);
|
||||
|
|
@ -211,6 +211,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
|
|||
clk_flags = clk_hw_get_flags(hw);
|
||||
p = clk_hw_get_parent_by_index(hw, index);
|
||||
if (clk_flags & CLK_SET_RATE_PARENT) {
|
||||
rate = f->freq;
|
||||
if (f->pre_div) {
|
||||
rate /= 2;
|
||||
rate *= f->pre_div + 1;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
|
|
@ -245,7 +246,7 @@ static int __init sp804_of_init(struct device_node *np)
|
|||
clk1 = NULL;
|
||||
|
||||
/* Get the 2nd clock if the timer has 3 timer clocks */
|
||||
if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
|
||||
if (of_clk_get_parent_count(np) == 3) {
|
||||
clk2 = of_clk_get(np, 1);
|
||||
if (IS_ERR(clk2)) {
|
||||
pr_err("sp804: %s clock not found: %d\n", np->name,
|
||||
|
|
|
|||
|
|
@ -12,12 +12,12 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
|
@ -1361,7 +1361,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
|
|||
goto gpiochip_error;
|
||||
}
|
||||
|
||||
ret = of_count_phandle_with_args(node, "clocks", "#clock-cells");
|
||||
ret = of_clk_get_parent_count(node);
|
||||
clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/regmap.h>
|
||||
|
|
@ -400,8 +401,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
|
|||
pd->info = pd_info;
|
||||
pd->pmu = pmu;
|
||||
|
||||
pd->num_clks = of_count_phandle_with_args(node, "clocks",
|
||||
"#clock-cells");
|
||||
pd->num_clks = of_clk_get_parent_count(node);
|
||||
if (pd->num_clks > 0) {
|
||||
pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
|
||||
sizeof(*pd->clks), GFP_KERNEL);
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include <linux/iopoll.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
|
|
@ -725,7 +726,7 @@ static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
|
|||
unsigned int i, count;
|
||||
int err;
|
||||
|
||||
count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
|
||||
count = of_clk_get_parent_count(np);
|
||||
if (count == 0)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Nuvoton NPCM7xx Clock Generator binding
|
||||
* clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
|
||||
*
|
||||
* Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
|
||||
#define __DT_BINDINGS_CLOCK_NPCM7XX_H
|
||||
|
||||
|
||||
#define NPCM7XX_CLK_CPU 0
|
||||
#define NPCM7XX_CLK_GFX_PIXEL 1
|
||||
#define NPCM7XX_CLK_MC 2
|
||||
#define NPCM7XX_CLK_ADC 3
|
||||
#define NPCM7XX_CLK_AHB 4
|
||||
#define NPCM7XX_CLK_TIMER 5
|
||||
#define NPCM7XX_CLK_UART 6
|
||||
#define NPCM7XX_CLK_MMC 7
|
||||
#define NPCM7XX_CLK_SPI3 8
|
||||
#define NPCM7XX_CLK_PCI 9
|
||||
#define NPCM7XX_CLK_AXI 10
|
||||
#define NPCM7XX_CLK_APB4 11
|
||||
#define NPCM7XX_CLK_APB3 12
|
||||
#define NPCM7XX_CLK_APB2 13
|
||||
#define NPCM7XX_CLK_APB1 14
|
||||
#define NPCM7XX_CLK_APB5 15
|
||||
#define NPCM7XX_CLK_CLKOUT 16
|
||||
#define NPCM7XX_CLK_GFX 17
|
||||
#define NPCM7XX_CLK_SU 18
|
||||
#define NPCM7XX_CLK_SU48 19
|
||||
#define NPCM7XX_CLK_SDHC 20
|
||||
#define NPCM7XX_CLK_SPI0 21
|
||||
#define NPCM7XX_CLK_SPIX 22
|
||||
|
||||
#define NPCM7XX_CLK_REFCLK 23
|
||||
#define NPCM7XX_CLK_SYSBYPCK 24
|
||||
#define NPCM7XX_CLK_MCBYPCK 25
|
||||
|
||||
#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
|
||||
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
|
||||
#define _DT_BINDINGS_CLK_MSM_RPMH_H
|
||||
|
||||
/* RPMh controlled clocks */
|
||||
#define RPMH_CXO_CLK 0
|
||||
#define RPMH_CXO_CLK_A 1
|
||||
#define RPMH_LN_BB_CLK2 2
|
||||
#define RPMH_LN_BB_CLK2_A 3
|
||||
#define RPMH_LN_BB_CLK3 4
|
||||
#define RPMH_LN_BB_CLK3_A 5
|
||||
#define RPMH_RF_CLK1 6
|
||||
#define RPMH_RF_CLK1_A 7
|
||||
#define RPMH_RF_CLK2 8
|
||||
#define RPMH_RF_CLK2_A 9
|
||||
#define RPMH_RF_CLK3 10
|
||||
#define RPMH_RF_CLK3_A 11
|
||||
|
||||
#endif
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_clk.h>
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
|
||||
|
|
@ -888,13 +889,10 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
|
|||
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
|
||||
struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
|
||||
void *data);
|
||||
unsigned int of_clk_get_parent_count(struct device_node *np);
|
||||
int of_clk_parent_fill(struct device_node *np, const char **parents,
|
||||
unsigned int size);
|
||||
const char *of_clk_get_parent_name(struct device_node *np, int index);
|
||||
int of_clk_detect_critical(struct device_node *np, int index,
|
||||
unsigned long *flags);
|
||||
void of_clk_init(const struct of_device_id *matches);
|
||||
|
||||
#else /* !CONFIG_OF */
|
||||
|
||||
|
|
@ -941,26 +939,16 @@ of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
|
|||
{
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
static inline unsigned int of_clk_get_parent_count(struct device_node *np)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int of_clk_parent_fill(struct device_node *np,
|
||||
const char **parents, unsigned int size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline const char *of_clk_get_parent_name(struct device_node *np,
|
||||
int index)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
static inline int of_clk_detect_critical(struct device_node *np, int index,
|
||||
unsigned long *flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void of_clk_init(const struct of_device_id *matches) {}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* OF clock helpers
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_OF_CLK_H
|
||||
#define __LINUX_OF_CLK_H
|
||||
|
||||
#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_OF)
|
||||
|
||||
unsigned int of_clk_get_parent_count(struct device_node *np);
|
||||
const char *of_clk_get_parent_name(struct device_node *np, int index);
|
||||
void of_clk_init(const struct of_device_id *matches);
|
||||
|
||||
#else /* !CONFIG_COMMON_CLK || !CONFIG_OF */
|
||||
|
||||
static inline unsigned int of_clk_get_parent_count(struct device_node *np)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline const char *of_clk_get_parent_name(struct device_node *np,
|
||||
int index)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
static inline void of_clk_init(const struct of_device_id *matches) {}
|
||||
|
||||
#endif /* !CONFIG_COMMON_CLK || !CONFIG_OF */
|
||||
|
||||
#endif /* __LINUX_OF_CLK_H */
|
||||
Loading…
Reference in New Issue