mirror of https://gitee.com/openkylin/linux.git
net: stmmac: Add descriptor related callbacks for XGMAC2
Add the descriptor related callbacks for the new IP block XGMAC2. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Cc: David S. Miller <davem@davemloft.net> Cc: Joao Pinto <jpinto@synopsys.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jose Abreu
David S. Miller
parent
d6ddfacd95
commit
874dfb65a4
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@ -5,7 +5,8 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
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dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o \
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mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \
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dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
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stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o $(stmmac-y)
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stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
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$(stmmac-y)
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# Ordering matters. Generic driver must be last.
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obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
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@ -195,4 +195,34 @@
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#define XGMAC_TPS BIT(1)
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#define XGMAC_TI BIT(0)
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/* Descriptors */
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#define XGMAC_TDES2_IOC BIT(31)
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#define XGMAC_TDES2_TTSE BIT(30)
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#define XGMAC_TDES2_B2L GENMASK(29, 16)
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#define XGMAC_TDES2_B2L_SHIFT 16
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#define XGMAC_TDES2_B1L GENMASK(13, 0)
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#define XGMAC_TDES3_OWN BIT(31)
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#define XGMAC_TDES3_CTXT BIT(30)
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#define XGMAC_TDES3_FD BIT(29)
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#define XGMAC_TDES3_LD BIT(28)
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#define XGMAC_TDES3_CPC GENMASK(27, 26)
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#define XGMAC_TDES3_CPC_SHIFT 26
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#define XGMAC_TDES3_TCMSSV BIT(26)
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#define XGMAC_TDES3_THL GENMASK(22, 19)
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#define XGMAC_TDES3_THL_SHIFT 19
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#define XGMAC_TDES3_TSE BIT(18)
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#define XGMAC_TDES3_CIC GENMASK(17, 16)
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#define XGMAC_TDES3_CIC_SHIFT 16
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#define XGMAC_TDES3_TPL GENMASK(17, 0)
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#define XGMAC_TDES3_FL GENMASK(14, 0)
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#define XGMAC_RDES3_OWN BIT(31)
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#define XGMAC_RDES3_CTXT BIT(30)
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#define XGMAC_RDES3_IOC BIT(30)
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#define XGMAC_RDES3_LD BIT(28)
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#define XGMAC_RDES3_CDA BIT(27)
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#define XGMAC_RDES3_ES BIT(15)
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#define XGMAC_RDES3_PL GENMASK(13, 0)
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#define XGMAC_RDES3_TSD BIT(6)
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#define XGMAC_RDES3_TSA BIT(4)
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#endif /* __STMMAC_DWXGMAC2_H__ */
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@ -0,0 +1,280 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
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* stmmac XGMAC support.
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*/
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#include <linux/stmmac.h>
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#include "common.h"
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#include "dwxgmac2.h"
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static int dwxgmac2_get_tx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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int ret = tx_done;
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if (unlikely(tdes3 & XGMAC_TDES3_OWN))
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return tx_dma_own;
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if (likely(!(tdes3 & XGMAC_TDES3_LD)))
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return tx_not_ls;
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return ret;
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}
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static int dwxgmac2_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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unsigned int rdes3 = le32_to_cpu(p->des3);
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int ret = good_frame;
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if (unlikely(rdes3 & XGMAC_RDES3_OWN))
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return dma_own;
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if (likely(!(rdes3 & XGMAC_RDES3_LD)))
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return discard_frame;
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if (unlikely(rdes3 & XGMAC_RDES3_ES))
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ret = discard_frame;
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return ret;
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}
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static int dwxgmac2_get_tx_len(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
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}
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static int dwxgmac2_get_tx_owner(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0;
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}
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static void dwxgmac2_set_tx_owner(struct dma_desc *p)
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{
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p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN);
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}
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static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
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{
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p->des3 = cpu_to_le32(XGMAC_RDES3_OWN);
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if (!disable_rx_ic)
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p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC);
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}
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static int dwxgmac2_get_tx_ls(struct dma_desc *p)
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{
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return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0;
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}
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static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)
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{
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return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL);
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}
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static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)
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{
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p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE);
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}
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static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)
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{
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return 0; /* Not supported */
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}
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static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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u64 ns = 0;
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ns += le32_to_cpu(p->des1) * 1000000000ULL;
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ns += le32_to_cpu(p->des0);
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*ts = ns;
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}
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static int dwxgmac2_rx_check_timestamp(void *desc)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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unsigned int rdes3 = le32_to_cpu(p->des3);
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bool desc_valid, ts_valid;
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desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT);
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ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA);
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if (likely(desc_valid && ts_valid))
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return 0;
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return -EINVAL;
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}
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static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
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u32 ats)
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{
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struct dma_desc *p = (struct dma_desc *)desc;
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unsigned int rdes3 = le32_to_cpu(p->des3);
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int ret = -EBUSY;
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if (likely(rdes3 & XGMAC_RDES3_CDA)) {
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ret = dwxgmac2_rx_check_timestamp(next_desc);
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if (ret)
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return ret;
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}
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return ret;
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}
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static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
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int mode, int end)
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{
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dwxgmac2_set_rx_owner(p, disable_rx_ic);
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}
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static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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bool csum_flag, int mode, bool tx_own,
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bool ls, unsigned int tot_pkt_len)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
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tdes3 = tot_pkt_len & XGMAC_TDES3_FL;
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if (is_fs)
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tdes3 |= XGMAC_TDES3_FD;
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else
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tdes3 &= ~XGMAC_TDES3_FD;
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if (csum_flag)
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tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
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else
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tdes3 &= ~XGMAC_TDES3_CIC;
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if (ls)
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tdes3 |= XGMAC_TDES3_LD;
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else
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tdes3 &= ~XGMAC_TDES3_LD;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= XGMAC_TDES3_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des3 = cpu_to_le32(tdes3);
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}
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static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
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int len1, int len2, bool tx_own,
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bool ls, unsigned int tcphdrlen,
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unsigned int tcppayloadlen)
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{
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unsigned int tdes3 = le32_to_cpu(p->des3);
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if (len1)
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p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
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if (len2)
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p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
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XGMAC_TDES2_B2L);
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if (is_fs) {
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tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
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tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
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XGMAC_TDES3_THL;
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tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
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} else {
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tdes3 &= ~XGMAC_TDES3_FD;
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}
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if (ls)
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tdes3 |= XGMAC_TDES3_LD;
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else
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tdes3 &= ~XGMAC_TDES3_LD;
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/* Finally set the OWN bit. Later the DMA will start! */
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if (tx_own)
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tdes3 |= XGMAC_TDES3_OWN;
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if (is_fs && tx_own)
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/* When the own bit, for the first frame, has to be set, all
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* descriptors for the same frame has to be set before, to
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* avoid race condition.
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*/
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dma_wmb();
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p->des3 = cpu_to_le32(tdes3);
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}
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static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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static void dwxgmac2_set_tx_ic(struct dma_desc *p)
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{
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p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC);
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}
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static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = cpu_to_le32(mss);
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p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
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}
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static void dwxgmac2_get_addr(struct dma_desc *p, unsigned int *addr)
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{
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*addr = le32_to_cpu(p->des0);
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}
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static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
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{
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p->des0 = cpu_to_le32(addr);
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p->des1 = 0;
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}
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static void dwxgmac2_clear(struct dma_desc *p)
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{
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p->des0 = 0;
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p->des1 = 0;
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p->des2 = 0;
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p->des3 = 0;
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}
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const struct stmmac_desc_ops dwxgmac210_desc_ops = {
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.tx_status = dwxgmac2_get_tx_status,
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.rx_status = dwxgmac2_get_rx_status,
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.get_tx_len = dwxgmac2_get_tx_len,
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.get_tx_owner = dwxgmac2_get_tx_owner,
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.set_tx_owner = dwxgmac2_set_tx_owner,
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.set_rx_owner = dwxgmac2_set_rx_owner,
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.get_tx_ls = dwxgmac2_get_tx_ls,
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.get_rx_frame_len = dwxgmac2_get_rx_frame_len,
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.enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,
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.get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,
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.get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,
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.get_timestamp = dwxgmac2_get_timestamp,
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.set_tx_ic = dwxgmac2_set_tx_ic,
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.prepare_tx_desc = dwxgmac2_prepare_tx_desc,
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.prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,
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.release_tx_desc = dwxgmac2_release_tx_desc,
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.init_rx_desc = dwxgmac2_init_rx_desc,
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.init_tx_desc = dwxgmac2_init_tx_desc,
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.set_mss = dwxgmac2_set_mss,
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.get_addr = dwxgmac2_get_addr,
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.set_addr = dwxgmac2_set_addr,
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.clear = dwxgmac2_clear,
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};
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@ -196,7 +196,7 @@ static const struct stmmac_hwif_entry {
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.ptp_off = 0,
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.mmc_off = 0,
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},
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.desc = NULL,
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.desc = &dwxgmac210_desc_ops,
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.dma = &dwxgmac210_dma_ops,
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.mac = &dwxgmac210_ops,
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.hwtimestamp = NULL,
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@ -481,6 +481,7 @@ extern const struct stmmac_ops dwmac510_ops;
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extern const struct stmmac_tc_ops dwmac510_tc_ops;
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extern const struct stmmac_ops dwxgmac210_ops;
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extern const struct stmmac_dma_ops dwxgmac210_dma_ops;
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extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
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#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */
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#define GMAC4_VERSION 0x00000110 /* GMAC4+ CORE Version */
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