openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

DaVinci SoC support updates for v4.18 

Mainly contains patches to move NAND chipselect to platform data
 (currently platform device id is being used). These patches have
 been acked by NAND maintainer and because of the driver dependency
 an immutable branch has been provided to Boris.
 
 The other patch is to remove an unnecessary postcore_initcall() on
 DM644x which is needed for common clock framework conversion.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJa/DYkAAoJEGFBu2jqvgRN3nQP/1IGbkmkCMtBRJcni7Es+x2p
 ntxG+NylyyQPMseZNPk3k1MBP9g9+kecpt22p/SDJVgY93+UU90UcUO+WSkqBEiy
 E/r+Mzj0EYmyY48dFo5v6dv5ED7lGSqtT0PywA5JCuVJ7Mzs3uHeBlKvhWgdcuSw
 McmjXLuyjHybXbpVuDFZ1vSDfmpMO2NskLtpIjIMR8Hk7pNXv+/6FEM5nJiQzSmO
 rIMdbEr4+Oqk+y5dWEY4GptSeCIOWiUrjQY3Hi8sLvUc7NVAsOchXcfnDeAI7otJ
 NvI2SOgmqiMHmoeWdxAlttt/guhUInWE2HOjGuCs/QEzx5ZXk1xsPAevvcjwtWdz
 C4bEK8nMLnXZ6Qd/vXSlQOlGhCBhxCms4pz7VJMeWdG1VXOIU7I7RYScPklA0UfA
 SUaHwrdvHOCMy0k3fbiPsv/vxwGvWZxsBDG5QF2geqQufo4lZMS6WgvB83Z5900Q
 rw+51Y44G8YpXlZKQrOZ+QzP4PP14FV/BuWeoBy+xXEZZSRghwJrADJcSI/+2KA9
 nCcxJgy66wJV4e96e4EXXRbyeVZjGmIp6gyMQsK67bAQ9/Kak4Dtv2VmI7ugbBcl
 HAFWfmXgC23+jYKTLQIZOPub8qaBIAx1zkKs+LWWoHW482QoHHLn7j9Dw26RKwST
 4smKyrDuM7NoxLZhnwrl
 =iWsm
 -----END PGP SIGNATURE-----

Merge tag 'davinci-for-v4.18/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

DaVinci SoC support updates for v4.18

Mainly contains patches to move NAND chipselect to platform data
(currently platform device id is being used). These patches have
been acked by NAND maintainer and because of the driver dependency
an immutable branch has been provided to Boris.

The other patch is to remove an unnecessary postcore_initcall() on
DM644x which is needed for common clock framework conversion.

* tag 'davinci-for-v4.18/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: dm644x: remove unnecessary postcore_initcall()
  ARM: davinci: aemif: stop using pdev->id as nand chipselect
  mtd: rawnand: davinci: stop using pdev->id as chipselect
  ARM: davinci: neuros-osd2: specify the chipselect in davinci_nand_pdata
  ARM: davinci: dm646x-evm: specify the chipselect in davinci_nand_pdata
  ARM: davinci: mityomapl138: specify the chipselect in davinci_nand_pdata
  ARM: davinci: dm644x-evm: specify the chipselect in davinci_nand_pdata
  ARM: davinci: dm365-evm: specify the chipselect in davinci_nand_pdata
  ARM: davinci: dm355-leopard: specify the chipselect in davinci_nand_pdata
  ARM: davinci: dm355-evm: specify the chipselect in davinci_nand_pdata
  ARM: davinci: da850-evm: specify the chipselect in davinci_nand_pdata
  ARM: davinci: da830-evm: specify the chipselect in davinci_nand_pdata
  mtd: rawnand: davinci: store the core chipselect number in platform data

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-05-25 04:57:56 -07:00
parent 3a19f20c5a ccfadbb759
commit 8787ad3563
15 changed files with 36 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/mach-davinci/aemif.c
View File

@ -189,7 +189,7 @@ int davinci_aemif_setup(struct platform_device *pdev)
* Setup Async configuration register in case we did not boot
* from NAND and so bootloader did not bother to set it up.
*/
val = davinci_aemif_readl(base, A1CR_OFFSET + pdev->id * 4);
val = davinci_aemif_readl(base, A1CR_OFFSET + pdata->core_chipsel * 4);
/*
* Extended Wait is not valid and Select Strobe mode is not
* used
@ -198,13 +198,13 @@ int davinci_aemif_setup(struct platform_device *pdev)
if (pdata->options & NAND_BUSWIDTH_16)
val |= 0x1;
davinci_aemif_writel(base, A1CR_OFFSET + pdev->id * 4, val);
davinci_aemif_writel(base, A1CR_OFFSET + pdata->core_chipsel * 4, val);
clkrate = clk_get_rate(clk);
if (pdata->timing)
ret = davinci_aemif_setup_timing(pdata->timing, base, pdev->id,
clkrate);
ret = davinci_aemif_setup_timing(pdata->timing, base,
pdata->core_chipsel, clkrate);
if (ret < 0)
dev_dbg(&pdev->dev, "NAND timing values setup fail\n");

1
arch/arm/mach-davinci/board-da830-evm.c
View File

@ -310,6 +310,7 @@ static struct davinci_aemif_timing da830_evm_nandflash_timing = {
};
static struct davinci_nand_pdata da830_evm_nand_pdata = {
.core_chipsel = 1,
.parts = da830_evm_nand_partitions,
.nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
.ecc_mode = NAND_ECC_HW,

1
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -244,6 +244,7 @@ static struct davinci_aemif_timing da850_evm_nandflash_timing = {
};
static struct davinci_nand_pdata da850_evm_nandflash_data = {
.core_chipsel = 1,
.parts = da850_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
.ecc_mode = NAND_ECC_HW,

1
arch/arm/mach-davinci/board-dm355-evm.c
View File

@ -77,6 +77,7 @@ static struct mtd_partition davinci_nand_partitions[] = {
};
static struct davinci_nand_pdata davinci_nand_data = {
.core_chipsel = 0,
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),

1
arch/arm/mach-davinci/board-dm355-leopard.c
View File

@ -72,6 +72,7 @@ static struct mtd_partition davinci_nand_partitions[] = {
};
static struct davinci_nand_pdata davinci_nand_data = {
.core_chipsel = 0,
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),

1
arch/arm/mach-davinci/board-dm365-evm.c
View File

@ -138,6 +138,7 @@ static struct mtd_partition davinci_nand_partitions[] = {
};
static struct davinci_nand_pdata davinci_nand_data = {
.core_chipsel = 0,
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),

3
arch/arm/mach-davinci/board-dm644x-evm.c
View File

@ -152,6 +152,7 @@ static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
};
static struct davinci_nand_pdata davinci_evm_nandflash_data = {
.core_chipsel = 0,
.parts = davinci_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
.ecc_mode = NAND_ECC_HW,
@ -768,6 +769,8 @@ static __init void davinci_evm_init(void)
struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_init_devices();
ret = dm644x_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);

1
arch/arm/mach-davinci/board-dm646x-evm.c
View File

@ -84,6 +84,7 @@ static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
};
static struct davinci_nand_pdata davinci_nand_data = {
.core_chipsel = 0,
.mask_cle = 0x80000,
.mask_ale = 0x40000,
.parts = davinci_nand_partitions,

1
arch/arm/mach-davinci/board-mityomapl138.c
View File

@ -400,6 +400,7 @@ static struct mtd_partition mityomapl138_nandflash_partition[] = {
};
static struct davinci_nand_pdata mityomapl138_nandflash_data = {
.core_chipsel = 1,
.parts = mityomapl138_nandflash_partition,
.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
.ecc_mode = NAND_ECC_HW,

3
arch/arm/mach-davinci/board-neuros-osd2.c
View File

@ -87,6 +87,7 @@ static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
};
static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
.core_chipsel = 0,
.parts = davinci_ntosd2_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
.ecc_mode = NAND_ECC_HW,
@ -174,6 +175,8 @@ static __init void davinci_ntosd2_init(void)
struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_init_devices();
ret = dm644x_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);

2
arch/arm/mach-davinci/board-sffsdr.c
View File

@ -134,6 +134,8 @@ static __init void davinci_sffsdr_init(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
dm644x_init_devices();
platform_add_devices(davinci_sffsdr_devices,
ARRAY_SIZE(davinci_sffsdr_devices));
sffsdr_init_i2c();

1
arch/arm/mach-davinci/davinci.h
View File

@ -104,6 +104,7 @@ int dm365_gpio_register(void);
/* DM644x function declarations */
void dm644x_init(void);
void dm644x_init_devices(void);
void dm644x_init_time(void);
void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);

13
arch/arm/mach-davinci/dm644x.c
View File

@ -961,19 +961,14 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
return 0;
}
static int __init dm644x_init_devices(void)
void __init dm644x_init_devices(void)
{
struct platform_device *edma_pdev;
int ret = 0;
if (!cpu_is_davinci_dm644x())
return 0;
int ret;
edma_pdev = platform_device_register_full(&dm644x_edma_device);
if (IS_ERR(edma_pdev)) {
if (IS_ERR(edma_pdev))
pr_warn("%s: Failed to register eDMA\n", __func__);
return PTR_ERR(edma_pdev);
}
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
@ -982,6 +977,4 @@ static int __init dm644x_init_devices(void)
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
postcore_initcall(dm644x_init_devices);

6
drivers/mtd/nand/raw/davinci_nand.c
View File

@ -547,7 +547,7 @@ static struct davinci_nand_pdata
return ERR_PTR(-ENOMEM);
if (!of_property_read_u32(pdev->dev.of_node,
"ti,davinci-chipselect", &prop))
pdev->id = prop;
pdata->core_chipsel = prop;
else
return ERR_PTR(-EINVAL);
@ -629,7 +629,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
return -ENODEV;
/* which external chipselect will we be managing? */
if (pdev->id < 0 || pdev->id > 3)
if (pdata->core_chipsel < 0 || pdata->core_chipsel > 3)
return -ENODEV;
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
@ -685,7 +685,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
info->ioaddr = (uint32_t __force) vaddr;
info->current_cs = info->ioaddr;
info->core_chipsel = pdev->id;
info->core_chipsel = pdata->core_chipsel;
info->mask_chipsel = pdata->mask_chipsel;
/* use nandboot-capable ALE/CLE masks by default */

10
include/linux/platform_data/mtd-davinci.h
View File

@ -56,6 +56,16 @@ struct davinci_nand_pdata { /* platform_data */
uint32_t mask_ale;
uint32_t mask_cle;
/*
* 0-indexed chip-select number of the asynchronous
* interface to which the NAND device has been connected.
*
* So, if you have NAND connected to CS3 of DA850, you
* will pass '1' here. Since the asynchronous interface
* on DA850 starts from CS2.
*/
uint32_t core_chipsel;
/* for packages using two chipselects */
uint32_t mask_chipsel;