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ARM: SoC platform changes 

New and updated SoC support. Also included are some cleanups where the
 platform maintainers hadn't separated cleanups from new developent in
 separate branches.
 
 Some of the larger things worth pointing out:
 
 - A large set of changes from Alexandre Belloni and Nicolas Ferre
   preparing at91 platforms for multiplatform and cleaning up quite a
   bit in the process.
 - Removal of CSR's "Marco" SoC platform that never made it out to the
   market. We love seeing these since it means the vendor published
   support before product was out, which is exactly what we want!
 
 New platforms this release are:
 
 - Conexant Digicolor (CX92755 SoC)
 - Hisilicon HiP01 SoC
 - CSR/sirf Atlas7 SoC
 - ST STiH418 SoC
 - Common code changes for Nvidia Tegra132 (64-bit SoC)
 
 We're seeing more and more platforms having a harder time labelling
 changes as cleanups vs new development -- which is a good sign that
 we've come quite far on the cleanup effort. So over time we might start
 combining the cleanup and new-development branches more.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New and updated SoC support.  Also included are some cleanups where
  the platform maintainers hadn't separated cleanups from new developent
  in separate branches.

  Some of the larger things worth pointing out:

   - A large set of changes from Alexandre Belloni and Nicolas Ferre
     preparing at91 platforms for multiplatform and cleaning up quite a
     bit in the process.

   - Removal of CSR's "Marco" SoC platform that never made it out to the
     market.  We love seeing these since it means the vendor published
     support before product was out, which is exactly what we want!

  New platforms this release are:

   - Conexant Digicolor (CX92755 SoC)
   - Hisilicon HiP01 SoC
   - CSR/sirf Atlas7 SoC
   - ST STiH418 SoC
   - Common code changes for Nvidia Tegra132 (64-bit SoC)

  We're seeing more and more platforms having a harder time labelling
  changes as cleanups vs new development -- which is a good sign that
  we've come quite far on the cleanup effort.  So over time we might
  start combining the cleanup and new-development branches more"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
  ARM: at91/trivial: unify functions and machine names
  ARM: at91: remove at91_dt_initialize and machine init_early()
  ARM: at91: change board files into SoC files
  ARM: at91: remove at91_boot_soc
  ARM: at91: move alternative initial mapping to board-dt-sama5.c
  ARM: at91: merge all SOC_AT91SAM9xxx
  ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
  ARM: digicolor: select syscon and timer
  ARM: zynq: Simplify SLCR initialization
  ARM: zynq: PM: Fixed simple typo.
  ARM: zynq: Setup default gpio number for Xilinx Zynq
  ARM: digicolor: add low level debug support
  ARM: initial support for Conexant Digicolor CX92755 SoC
  ARM: OMAP2+: Add dm816x hwmod support
  ARM: OMAP2+: Add clock domain support for dm816x
  ARM: OMAP2+: Add board-generic.c entry for ti81xx
  ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
  ARM: at91: remove unused mach/system_rev.h
  ARM: at91: stop using HAVE_AT91_DBGUx
  ARM: at91: fix ordering of SRAM and PM initialization
  ...
This commit is contained in:
Linus Torvalds 2015-02-17 09:27:54 -08:00
parent ea7531ac4a df1a668125
commit 878ba61aa9
137 changed files with 4078 additions and 1380 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/arm/sti/stih418-overview.txt Normal file
View File

@ -0,0 +1,20 @@
STiH418 Overview
================
Introduction
------------
The STiH418 is the new generation of SoC for UHDp60 set-top boxes
and server/connected client application for satellite, cable, terrestrial
and IP-STB markets.
Features
- ARM Cortex-A9 1.5 GHz quad core CPU (28nm)
- SATA2, USB 3.0, PCIe, Gbit Ethernet
- HEVC L5.1 Main 10
- VP9
Document Author
---------------
Maxime Coquelin <maxime.coquelin@st.com>, (c) 2015 ST Microelectronics

1
Documentation/arm/sunxi/README
View File

@ -50,7 +50,6 @@ SunXi family
http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf
- Allwinner A31s (sun6i)
+ Not Supported
+ Datasheet
http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf
+ User Manual

17
Documentation/devicetree/bindings/arm/atmel-at91.txt
View File

@ -24,6 +24,7 @@ compatible: must be one of:
o "atmel,at91sam9g45"
o "atmel,at91sam9n12"
o "atmel,at91sam9rl"
o "atmel,at91sam9xe"
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
SoC family:
o "atmel,sama5d3" shall be extended with the specific SoC compatible:
@ -136,3 +137,19 @@ Example:
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
};
Special Function Registers (SFR)
Special Function Registers (SFR) manage specific aspects of the integrated
memory, bridge implementations, processor and other functionality not controlled
elsewhere.
required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon".
<chip> can be "sama5d3" or "sama5d4".
- reg: Should contain registers location and length
sfr@f0038000 {
compatible = "atmel,sama5d3-sfr", "syscon";
reg = <0xf0038000 0x60>;
};

12
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -75,6 +75,18 @@ i.MX6q generic board
Required root node properties:
- compatible = "fsl,imx6q";
Freescale Vybrid Platform Device Tree Bindings
----------------------------------------------
For the Vybrid SoC familiy all variants with DDR controller are supported,
which is the VF5xx and VF6xx series. Out of historical reasons, in most
places the kernel uses vf610 to refer to the whole familiy.
Required root node compatible property (one of them):
- compatible = "fsl,vf500";
- compatible = "fsl,vf510";
- compatible = "fsl,vf600";
- compatible = "fsl,vf610";
Freescale LS1021A Platform Device Tree Bindings
------------------------------------------------

16
Documentation/devicetree/bindings/arm/rockchip/pmu-sram.txt Normal file
View File

@ -0,0 +1,16 @@
Rockchip SRAM for pmu:
------------------------------
The sram of pmu is used to store the function of resume from maskrom(the 1st
level loader). This is a common use of the "pmu-sram" because it keeps power
even in low power states in the system.
Required node properties:
- compatible : should be "rockchip,rk3288-pmu-sram"
- reg : physical base address and the size of the registers window
Example:
sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
reg = <0xff720000 0x1000>;
};

4
Documentation/devicetree/bindings/arm/sti.txt
View File

@ -13,3 +13,7 @@ Boards with the ST STiH407 SoC shall have the following properties:
Required root node property:
compatible = "st,stih407";
Boards with the ST STiH418 SoC shall have the following properties:
Required root node property:
compatible = "st,stih418";

26
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
View File

@ -51,6 +51,23 @@ Required properties when nvidia,suspend-mode=<0>:
sleep mode, the warm boot code will restore some PLLs, clocks and then
bring up CPU0 for resuming the system.
Hardware-triggered thermal reset:
On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
hardware-triggered thermal reset will be enabled.
Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
Tegra K1 Technical Reference Manual.
- nvidia,bus-addr : Bus address of the PMU on the I2C bus
- nvidia,reg-addr : I2C register address to write poweroff command to
- nvidia,reg-data : Poweroff command to write to PMU
Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
Defaults to 0. Valid values are described in section 12.5.2
"Pinmux Support" of the Tegra4 Technical Reference Manual.
Example:
/ SoC dts including file
@ -72,6 +89,15 @@ pmc@7000f400 {
/ Tegra board dts file
{
...
pmc@7000f400 {
i2c-thermtrip {
nvidia,i2c-controller-id = <4>;
nvidia,bus-addr = <0x40>;
nvidia,reg-addr = <0x36>;
nvidia,reg-data = <0x2>;
};
};
...
clocks {
compatible = "simple-bus";

3
MAINTAINERS
View File

@ -1310,10 +1310,13 @@ S: Maintained
ARM/QUALCOMM SUPPORT
M: Kumar Gala <galak@codeaurora.org>
M: Andy Gross <agross@codeaurora.org>
M: David Brown <davidb@codeaurora.org>
L: linux-arm-msm@vger.kernel.org
L: linux-soc@vger.kernel.org
S: Maintained
F: arch/arm/mach-qcom/
F: drivers/soc/qcom/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
ARM/RADISYS ENP2611 MACHINE SUPPORT

4
arch/arm/Kconfig
View File

@ -860,6 +860,8 @@ source "arch/arm/mach-cns3xxx/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-digicolor/Kconfig"
source "arch/arm/mach-dove/Kconfig"
source "arch/arm/mach-ep93xx/Kconfig"
@ -1493,7 +1495,7 @@ config ARM_PSCI
# selected platforms.
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
default 416 if ARCH_SUNXI

114
arch/arm/Kconfig.debug
View File

@ -117,17 +117,20 @@ choice
config AT91_DEBUG_LL_DBGU0
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10, 9rl, 9x5, 9n12"
select DEBUG_AT91_UART
depends on HAVE_AT91_DBGU0
depends on ARCH_AT91
depends on SOC_AT91RM9200 || SOC_AT91SAM9
config AT91_DEBUG_LL_DBGU1
bool "Kernel low-level debugging on 9263, 9g45 and sama5d3"
select DEBUG_AT91_UART
depends on HAVE_AT91_DBGU1
depends on ARCH_AT91
depends on SOC_AT91SAM9 || SOC_SAMA5
config AT91_DEBUG_LL_DBGU2
bool "Kernel low-level debugging on sama5d4"
select DEBUG_AT91_UART
depends on HAVE_AT91_DBGU2
depends on ARCH_AT91
depends on SOC_SAMA5
config DEBUG_BCM2835
bool "Kernel low-level debugging on BCM2835 PL011 UART"
@ -244,6 +247,13 @@ choice
Say Y here if you want the debug print routines to direct
their output to the serial port in the DC21285 (Footbridge).
config DEBUG_DIGICOLOR_UA0
bool "Kernel low-level debugging messages via Digicolor UA0"
depends on ARCH_DIGICOLOR
help
Say Y here if you want the debug print routines to direct
their output to the UA0 serial port in the CX92755.
config DEBUG_FOOTBRIDGE_COM1
bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
depends on FOOTBRIDGE
@ -275,6 +285,14 @@ choice
Say Y here if you want the debug print routines to direct
their output to the UART on Highbank based devices.
config DEBUG_HIP01_UART
bool "Hisilicon Hip01 Debug UART"
depends on ARCH_HIP01
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on HIP01 UART.
config DEBUG_HIP04_UART
bool "Hisilicon HiP04 Debug UART"
depends on ARCH_HIP04
@ -437,7 +455,7 @@ choice
Say Y here if you want the debug print routines to direct
their output to the serial port on MSM devices.
ARCH DEBUG_UART_PHYS DEBUG_UART_BASE #
ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT #
MSM7X00A, QSD8X50 0xa9a00000 0xe1000000 UART1
MSM7X00A, QSD8X50 0xa9b00000 0xe1000000 UART2
MSM7X00A, QSD8X50 0xa9c00000 0xe1000000 UART3
@ -456,7 +474,8 @@ choice
Say Y here if you want the debug print routines to direct
their output to the serial port on Qualcomm devices.
ARCH DEBUG_UART_PHYS DEBUG_UART_BASE
ARCH DEBUG_UART_PHYS DEBUG_UART_VIRT
APQ8064 0x16640000 0xf0040000
APQ8084 0xf995e000 0xfa75e000
MSM8X60 0x19c40000 0xf0040000
MSM8960 0x16440000 0xf0040000
@ -465,13 +484,13 @@ choice
Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
options based on your needs.
config DEBUG_MVEBU_UART
bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
config DEBUG_MVEBU_UART0
bool "Kernel low-level debugging messages via MVEBU UART0 (old bootloaders)"
depends on ARCH_MVEBU
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms.
on MVEBU based platforms on UART0.
This option should be used with the old bootloaders
that left the internal registers mapped at
@ -484,13 +503,28 @@ choice
when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all.
config DEBUG_MVEBU_UART_ALTERNATE
bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
config DEBUG_MVEBU_UART0_ALTERNATE
bool "Kernel low-level debugging messages via MVEBU UART0 (new bootloaders)"
depends on ARCH_MVEBU
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms.
on MVEBU based platforms on UART0.
This option should be used with the new bootloaders
that remap the internal registers at 0xf1000000.
If the wrong DEBUG_MVEBU_UART* option is selected,
when u-boot hands over to the kernel, the system
silently crashes, with no serial output at all.
config DEBUG_MVEBU_UART1_ALTERNATE
bool "Kernel low-level debugging messages via MVEBU UART1 (new bootloaders)"
depends on ARCH_MVEBU
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on MVEBU based platforms on UART1.
This option should be used with the new bootloaders
that remap the internal registers at 0xf1000000.
@ -981,16 +1015,28 @@ choice
config DEBUG_SIRFPRIMA2_UART1
bool "Kernel low-level debugging messages via SiRFprimaII UART1"
depends on ARCH_PRIMA2
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFprimaII devices.
config DEBUG_SIRFMARCO_UART1
bool "Kernel low-level debugging messages via SiRFmarco UART1"
depends on ARCH_MARCO
config DEBUG_SIRFATLAS7_UART0
bool "Kernel low-level debugging messages via SiRFatlas7 UART0"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFmarco devices.
their output to the uart0 port on SiRFATLAS7 devices.The uart0
is used on SiRFATLAS7 as a extra debug port.sometimes an extra
debug port can be very useful.
config DEBUG_SIRFATLAS7_UART1
bool "Kernel low-level debugging messages via SiRFatlas7 UART1"
depends on ARCH_ATLAS7
select DEBUG_SIRFSOC_UART
help
Say Y here if you want the debug print routines to direct
their output to the uart1 port on SiRFATLAS7 devices.
config STIH41X_DEBUG_ASC2
bool "Use StiH415/416 ASC2 UART for low-level debug"
@ -1038,7 +1084,7 @@ choice
for Mediatek mt6589 based platforms on UART0.
config DEBUG_MT8127_UART0
bool "Mediatek mt8127 UART0"
bool "Mediatek mt8127/mt6592 UART0"
depends on ARCH_MEDIATEK
select DEBUG_UART_8250
help
@ -1165,6 +1211,10 @@ choice
endchoice
config DEBUG_AT91_UART
bool
depends on ARCH_AT91
config DEBUG_EXYNOS_UART
bool
@ -1217,12 +1267,15 @@ config DEBUG_STI_UART
bool
depends on ARCH_STI
config DEBUG_SIRFSOC_UART
bool
depends on ARCH_SIRF
config DEBUG_LL_INCLUDE
string
default "debug/sa1100.S" if DEBUG_SA1100
default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
default "debug/at91.S" if AT91_DEBUG_LL_DBGU0 || AT91_DEBUG_LL_DBGU1 || \
AT91_DEBUG_LL_DBGU2
default "debug/at91.S" if DEBUG_AT91_UART
default "debug/asm9260.S" if DEBUG_ASM9260_UART
default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
default "debug/meson.S" if DEBUG_MESON_UARTAO
@ -1255,7 +1308,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
default "debug/s5pv210.S" if DEBUG_S5PV210_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/sirf.S" if DEBUG_SIRFSOC_UART
default "debug/sti.S" if DEBUG_STI_UART
default "debug/tegra.S" if DEBUG_TEGRA_UART
default "debug/ux500.S" if DEBUG_UX500_UART
@ -1264,6 +1317,7 @@ config DEBUG_LL_INCLUDE
default "debug/vt8500.S" if DEBUG_VT8500_UART0
default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX
default "debug/digicolor.S" if DEBUG_DIGICOLOR_UA0
default "mach/debug-macro.S"
# Compatibility options for PL01x
@ -1307,7 +1361,10 @@ config DEBUG_UART_PHYS
default 0x11009000 if DEBUG_MT8135_UART3
default 0x16000000 if ARCH_INTEGRATOR
default 0x18000300 if DEBUG_BCM_5301X
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
default 0x18020000 if DEBUG_SIRFATLAS7_UART1
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
default 0x20001000 if DEBUG_HIP01_UART
default 0x20060000 if DEBUG_RK29_UART0
default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0x20068000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
@ -1332,12 +1389,13 @@ config DEBUG_UART_PHYS
default 0x808c0000 if ARCH_EP93XX
default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
default 0xa9a00000 if DEBUG_MSM_UART
default 0xb0060000 if DEBUG_SIRFPRIMA2_UART1
default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
default 0xc0013000 if DEBUG_U300_UART
default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
default 0xd0000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
default 0xd0012000 if DEBUG_MVEBU_UART
default 0xd0012000 if DEBUG_MVEBU_UART0
default 0xc81004c0 if DEBUG_MESON_UARTAO
default 0xd4017000 if DEBUG_MMP_UART2
default 0xd4018000 if DEBUG_MMP_UART3
@ -1351,7 +1409,8 @@ config DEBUG_UART_PHYS
default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xf0000be0 if ARCH_EBSA110
default 0xf040ab00 if DEBUG_BRCMSTB_UART
default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
ARCH_ORION5X
default 0xf7fc9000 if DEBUG_BERLIN_UART
@ -1380,7 +1439,8 @@ config DEBUG_UART_PHYS
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART
DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
@ -1438,8 +1498,12 @@ config DEBUG_UART_VIRT
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
default 0xfec02000 if DEBUG_SOCFPGA_UART
default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE
default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE
default 0xfec10000 if DEBUG_SIRFATLAS7_UART0
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
default 0xfec20000 if DEBUG_SIRFATLAS7_UART1
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
@ -1458,12 +1522,14 @@ config DEBUG_UART_VIRT
default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
default 0xfefff700 if ARCH_IOP33X
default 0xff003000 if DEBUG_U300_UART
default 0xffd01000 if DEBUG_HIP01_UART
default DEBUG_UART_PHYS if !MMU
depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \
DEBUG_MSM_UART || DEBUG_NETX_UART || \
DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART
DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"

12
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -66,6 +66,11 @@ main_xtal: main_xtal {
};
};
sram: sram@00200000 {
compatible = "mmio-sram";
reg = <0x00200000 0x4000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -356,6 +361,13 @@ st: timer@fffffd00 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
};
rtc: rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffa0000 0x100>;

4
arch/arm/boot/dts/at91rm9200ek.dts
View File

@ -77,6 +77,10 @@ mtd_dataflash@0 {
dbgu: serial@fffff200 {
status = "okay";
};
rtc: rtc@fffffe00 {
status = "okay";
};
};
usb0: ohci@00300000 {

5
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -69,6 +69,11 @@ adc_op_clk: adc_op_clk{
};
};
sram0: sram@002ff000 {
compatible = "mmio-sram";
reg = <0x002ff000 0x2000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;

5
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -60,6 +60,11 @@ slow_xtal: slow_xtal {
};
};
sram: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x28000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;

12
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -62,6 +62,16 @@ slow_xtal: slow_xtal {
};
};
sram0: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x14000>;
};
sram1: sram@00500000 {
compatible = "mmio-sram";
reg = <0x00300000 0x4000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -294,7 +304,7 @@ ssc1_clk: ssc1_clk {
reg = <17>;
};
ac91_clk: ac97_clk {
ac97_clk: ac97_clk {
#clock-cells = <0>;
reg = <18>;
};

9
arch/arm/boot/dts/at91sam9g20.dtsi
View File

@ -16,6 +16,15 @@ memory {
reg = <0x20000000 0x08000000>;
};
sram0: sram@002ff000 {
status = "disabled";
};
sram1: sram@002fc000 {
compatible = "mmio-sram";
reg = <0x002fc000 0x8000>;
};
ahb {
apb {
i2c0: i2c@fffac000 {

7
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -74,6 +74,11 @@ adc_op_clk: adc_op_clk{
};
};
sram: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x10000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -1287,7 +1292,6 @@ usb0: ohci@00700000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
//TODO
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
status = "disabled";
@ -1297,7 +1301,6 @@ usb1: ehci@00800000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
//TODO
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
status = "disabled";

12
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -64,6 +64,11 @@ main_xtal: main_xtal {
};
};
sram: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x8000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -893,6 +898,13 @@ watchdog@fffffe40 {
status = "disabled";
};
rtc@fffffeb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
pwm0: pwm@f8034000 {
compatible = "atmel,at91sam9rl-pwm";
reg = <0xf8034000 0x300>;

5
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -70,6 +70,11 @@ adc_op_clk: adc_op_clk{
};
};
sram: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x10000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;

5
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -72,6 +72,11 @@ adc_op_clk: adc_op_clk{
};
};
sram: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x8000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;

60
arch/arm/boot/dts/at91sam9xe.dtsi Normal file
View File

@ -0,0 +1,60 @@
/*
* at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
*
* Copyright (C) 2015 Atmel,
* 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "at91sam9260.dtsi"
/ {
model = "Atmel AT91SAM9XE family SoC";
compatible = "atmel,at91sam9xe", "atmel,at91sam9260";
sram0: sram@002ff000 {
status = "disabled";
};
sram1: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x4000>;
};
};

2
arch/arm/boot/dts/ethernut5.dts
View File

@ -6,7 +6,7 @@
* Licensed under GPLv2.
*/
/dts-v1/;
#include "at91sam9260.dtsi"
#include "at91sam9xe.dtsi"
/ {
model = "Ethernut 5";

34
arch/arm/boot/dts/sama5d3.dtsi
View File

@ -78,6 +78,11 @@ adc_op_clk: adc_op_clk{
};
};
sram: sram@00300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x20000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -214,7 +219,20 @@ isi: isi@f0034000 {
compatible = "atmel,at91sam9g45-isi";
reg = <0xf0034000 0x4000>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
clocks = <&isi_clk>;
clock-names = "isi_clk";
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
sfr: sfr@f0038000 {
compatible = "atmel,sama5d3-sfr", "syscon";
reg = <0xf0038000 0x60>;
};
mmc1: mmc@f8000000 {
@ -545,7 +563,7 @@ pinctrl_i2c2: i2c2-0 {
};
isi {
pinctrl_isi: isi-0 {
pinctrl_isi_data_0_7: isi-0-data-0-7 {
atmel,pins =
<AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
@ -557,13 +575,19 @@ AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts
AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
};
pinctrl_isi_data_8_9: isi-0-data-8-9 {
atmel,pins =
<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
};
pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
pinctrl_isi_data_10_11: isi-0-data-10-11 {
atmel,pins =
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
};
};

1
arch/arm/boot/dts/sama5d3xcm.dtsi
View File

@ -122,6 +122,7 @@ leds {
d2 {
label = "d2";
gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */
linux,default-trigger = "heartbeat";
};
};
};

40
arch/arm/boot/dts/sama5d3xmb.dtsi
View File

@ -52,6 +52,29 @@ wm8904: wm8904@1a {
};
};
i2c1: i2c@f0018000 {
ov2640: camera@0x30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
clocks = <&pck1>;
clock-names = "xvclk";
assigned-clocks = <&pck1>;
assigned-clock-rates = <25000000>;
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
usart1: serial@f0020000 {
dmas = <0>, <0>; /* Do not use DMA for usart1 */
pinctrl-names = "default";
@ -60,8 +83,12 @@ usart1: serial@f0020000 {
};
isi: isi@f0034000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
port {
isi_0: endpoint {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
};
};
};
mmc1: mmc@f8000000 {
@ -117,12 +144,17 @@ pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
<AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
};
pinctrl_isi_reset: isi_reset-0 {
pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
atmel,pins =
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
};
pinctrl_sensor_reset: sensor_reset-0 {
atmel,pins =
<AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */
};
pinctrl_isi_power: isi_power-0 {
pinctrl_sensor_power: sensor_power-0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
};

10
arch/arm/boot/dts/sama5d4.dtsi
View File

@ -103,6 +103,11 @@ adc_op_clk: adc_op_clk{
};
};
ns_sram: sram@00210000 {
compatible = "mmio-sram";
reg = <0x00210000 0x10000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -870,6 +875,11 @@ i2c2: i2c@f8024000 {
status = "disabled";
};
sfr: sfr@f8028000 {
compatible = "atmel,sama5d4-sfr", "syscon";
reg = <0xf8028000 0x60>;
};
mmc1: mmc@fc000000 {
compatible = "atmel,hsmci";
reg = <0xfc000000 0x600>;

7
arch/arm/boot/dts/tegra124-jetson-tk1.dts
View File

@ -1673,6 +1673,13 @@ pmc@0,7000e400 {
nvidia,core-pwr-off-time = <61036>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
i2c-thermtrip {
nvidia,i2c-controller-id = <4>;
nvidia,bus-addr = <0x40>;
nvidia,reg-addr = <0x36>;
nvidia,reg-data = <0x2>;
};
};
/* Serial ATA */

10
arch/arm/configs/at91_dt_defconfig
View File

@ -15,15 +15,7 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91RM9200=y
CONFIG_SOC_AT91SAM9260=y
CONFIG_SOC_AT91SAM9261=y
CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9RL=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_SOC_AT91SAM9N12=y
CONFIG_MACH_AT91RM9200_DT=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_SOC_AT91SAM9=y
CONFIG_AT91_TIMER_HZ=128
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y

35
arch/arm/include/debug/digicolor.S Normal file
View File

@ -0,0 +1,35 @@
/*
* Debugging macro include header for Conexant Digicolor USART
*
* Copyright (C) 2014 Paradox Innovation Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#define UA0_STATUS 0x0742
#define UA0_EMI_REC 0x0744
#define UA0_STATUS_TX_READY 0x40
#ifdef CONFIG_DEBUG_UART_PHYS
.macro addruart, rp, rv, tmp
ldr \rp, =CONFIG_DEBUG_UART_PHYS
ldr \rv, =CONFIG_DEBUG_UART_VIRT
.endm
#endif
.macro senduart,rd,rx
strb \rd, [\rx, #UA0_EMI_REC]
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
1001: ldrb \rd, [\rx, #UA0_STATUS]
tst \rd, #UA0_STATUS_TX_READY
beq 1001b
.endm

6
arch/arm/include/debug/msm.S
View File

@ -23,6 +23,7 @@
.endm
.macro senduart, rd, rx
ARM_BE8(rev \rd, \rd )
#ifdef CONFIG_DEBUG_QCOM_UARTDM
@ Write the 1 character to UARTDM_TF
str \rd, [\rx, #0x70]
@ -35,24 +36,29 @@
#ifdef CONFIG_DEBUG_QCOM_UARTDM
@ check for TX_EMT in UARTDM_SR
ldr \rd, [\rx, #0x08]
ARM_BE8(rev \rd, \rd )
tst \rd, #0x08
bne 1002f
@ wait for TXREADY in UARTDM_ISR
1001: ldr \rd, [\rx, #0x14]
ARM_BE8(rev \rd, \rd )
tst \rd, #0x80
beq 1001b
1002:
@ Clear TX_READY by writing to the UARTDM_CR register
mov \rd, #0x300
ARM_BE8(rev \rd, \rd )
str \rd, [\rx, #0x10]
@ Write 0x1 to NCF register
mov \rd, #0x1
ARM_BE8(rev \rd, \rd )
str \rd, [\rx, #0x40]
@ UARTDM reg. Read to induce delay
ldr \rd, [\rx, #0x08]
#else
@ wait for TX_READY
1001: ldr \rd, [\rx, #0x08]
ARM_BE8(rev \rd, \rd )
tst \rd, #0x04
beq 1001b
#endif

30
arch/arm/include/debug/sirf.S
View File

@ -6,37 +6,33 @@
* Licensed under GPLv2 or later.
*/
#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
#define SIRFSOC_UART1_PA_BASE 0xb0060000
#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
#define SIRFSOC_UART1_PA_BASE 0xcc060000
#define SIRF_LLUART_TXFIFO_STATUS 0x0114
#define SIRF_LLUART_TXFIFO_DATA 0x0118
#define SIRF_LLUART_TXFIFO_FULL (1 << 5)
#ifdef CONFIG_DEBUG_SIRFATLAS7_UART0
#define SIRF_LLUART_TXFIFO_EMPTY (1 << 8)
#else
#define SIRFSOC_UART1_PA_BASE 0
#define SIRF_LLUART_TXFIFO_EMPTY (1 << 6)
#endif
#define SIRFSOC_UART1_VA_BASE 0xFEC60000
#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
#define SIRFSOC_UART_TXFIFO_DATA 0x0118
#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
.macro addruart, rp, rv, tmp
ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
ldr \rp, =CONFIG_DEBUG_UART_PHYS @ physical
ldr \rv, =CONFIG_DEBUG_UART_VIRT @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
str \rd, [\rx, #SIRF_LLUART_TXFIFO_DATA]
.endm
.macro busyuart,rd,rx
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
tst \rd, #SIRF_LLUART_TXFIFO_EMPTY
beq 1001b
.endm

112
arch/arm/mach-at91/Kconfig
View File

@ -6,15 +6,6 @@ config HAVE_AT91_UTMI
config HAVE_AT91_USB_CLK
bool
config HAVE_AT91_DBGU0
bool
config HAVE_AT91_DBGU1
bool
config HAVE_AT91_DBGU2
bool
config COMMON_CLK_AT91
bool
select COMMON_CLK
@ -25,15 +16,6 @@ config HAVE_AT91_SMD
config HAVE_AT91_H32MX
bool
config SOC_AT91SAM9
bool
select ATMEL_AIC_IRQ
select COMMON_CLK_AT91
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MEMORY
select ATMEL_SDRAMC
config SOC_SAMA5
bool
select ATMEL_AIC5_IRQ
@ -70,7 +52,6 @@ config SOC_SAMA5D3
bool "SAMA5D3 family"
select SOC_SAMA5
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU1
select HAVE_AT91_UTMI
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
@ -81,7 +62,6 @@ config SOC_SAMA5D3
config SOC_SAMA5D4
bool "SAMA5D4 family"
select SOC_SAMA5
select HAVE_AT91_DBGU2
select CLKSRC_MMIO
select CACHE_L2X0
select CACHE_PL310
@ -101,83 +81,45 @@ config SOC_AT91RM9200
select COMMON_CLK_AT91
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select HAVE_AT91_USB_CLK
config SOC_AT91SAM9260
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
select HAVE_AT91_DBGU0
select SOC_AT91SAM9
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
config SOC_AT91SAM9261
bool "AT91SAM9261 or AT91SAM9G10"
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
config SOC_AT91SAM9263
bool "AT91SAM9263"
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_USB_CLK
config SOC_AT91SAM9RL
bool "AT91SAM9RL"
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
config SOC_AT91SAM9G45
bool "AT91SAM9G45 or AT91SAM9M10 families"
select HAVE_AT91_DBGU1
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
config SOC_AT91SAM9X5
bool "AT91SAM9x5 family"
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_UTMI
config SOC_AT91SAM9
bool "AT91SAM9"
select ATMEL_AIC_IRQ
select ATMEL_SDRAMC
select COMMON_CLK_AT91
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
help
Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
This means that your SAM9 name finishes with a '5' (except if it is
AT91SAM9G45!).
This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
and AT91SAM9X35.
config SOC_AT91SAM9N12
bool "AT91SAM9N12 family"
select HAVE_AT91_DBGU0
select HAVE_AT91_UTMI
select HAVE_FB_ATMEL
select SOC_AT91SAM9
select HAVE_AT91_USB_CLK
select MEMORY
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
# ----------------------------------------------------------
Select this if you are using one of those Atmel SoC:
AT91SAM9260
AT91SAM9261
AT91SAM9263
AT91SAM9G15
AT91SAM9G20
AT91SAM9G25
AT91SAM9G35
AT91SAM9G45
AT91SAM9G46
AT91SAM9M10
AT91SAM9M11
AT91SAM9N12
AT91SAM9RL
AT91SAM9X25
AT91SAM9X35
AT91SAM9XE
endif # SOC_SAM_V4_V5
comment "AT91 Feature Selections"
config AT91_SLOW_CLOCK
bool "Suspend-to-RAM disables main oscillator"
select SRAM
depends on SUSPEND
help
Select this if you want Suspend-to-RAM to save the most power

18
arch/arm/mach-at91/Makefile
View File

@ -8,22 +8,8 @@ obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
# CPU-specific support
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o
obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o
obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o
obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o
obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o
obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
# AT91SAM board with device-tree
obj-$(CONFIG_SOC_AT91RM9200) += board-dt-rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += board-dt-sam9.o
# SAMA5 board with device-tree
obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o
# Power Management
obj-$(CONFIG_PM) += pm.o

66
arch/arm/mach-at91/at91rm9200.c
View File

@ -1,35 +1,33 @@
/*
* arch/arm/mach-at91/at91rm9200.c
* Setup code for AT91RM9200
*
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
* 2012 Joachim Eastwood <manabian@gmail.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk/at91_pmc.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/system_misc.h>
#include <mach/at91_st.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
static void at91rm9200_idle(void)
{
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
}
static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
{
/*
@ -39,23 +37,31 @@ static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
}
/* --------------------------------------------------------------------
* AT91RM9200 processor initialization
* -------------------------------------------------------------------- */
static void __init at91rm9200_map_io(void)
static void __init at91rm9200_dt_timer_init(void)
{
/* Map peripherals */
at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
of_clk_init(NULL);
at91rm9200_timer_init();
}
static void __init at91rm9200_initialize(void)
static void __init at91rm9200_dt_device_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
arm_pm_idle = at91rm9200_idle;
arm_pm_restart = at91rm9200_restart;
at91rm9200_pm_init();
}
AT91_SOC_START(at91rm9200)
.map_io = at91rm9200_map_io,
.init = at91rm9200_initialize,
AT91_SOC_END
static const char *at91rm9200_dt_board_compat[] __initconst = {
"atmel,at91rm9200",
NULL
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200")
.init_time = at91rm9200_dt_timer_init,
.map_io = at91_map_io,
.init_machine = at91rm9200_dt_device_init,
.dt_compat = at91rm9200_dt_board_compat,
MACHINE_END

87
arch/arm/mach-at91/at91sam9.c Normal file
View File

@ -0,0 +1,87 @@
/*
* Setup code for AT91SAM9
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk-provider.h>
#include <asm/system_misc.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "generic.h"
static void __init at91sam9_dt_device_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
arm_pm_idle = at91sam9_idle;
at91sam9260_pm_init();
}
static const char *at91_dt_board_compat[] __initconst = {
"atmel,at91sam9",
NULL
};
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
/* Maintainer: Atmel */
.map_io = at91_map_io,
.init_machine = at91sam9_dt_device_init,
.dt_compat = at91_dt_board_compat,
MACHINE_END
static void __init at91sam9g45_dt_device_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
arm_pm_idle = at91sam9_idle;
at91sam9g45_pm_init();
}
static const char *at91sam9g45_board_compat[] __initconst = {
"atmel,at91sam9g45",
NULL
};
DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
/* Maintainer: Atmel */
.map_io = at91_map_io,
.init_machine = at91sam9g45_dt_device_init,
.dt_compat = at91sam9g45_board_compat,
MACHINE_END
static void __init at91sam9x5_dt_device_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
arm_pm_idle = at91sam9_idle;
at91sam9x5_pm_init();
}
static const char *at91sam9x5_board_compat[] __initconst = {
"atmel,at91sam9x5",
"atmel,at91sam9n12",
NULL
};
DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
/* Maintainer: Atmel */
.map_io = at91_map_io,
.init_machine = at91sam9x5_dt_device_init,
.dt_compat = at91sam9x5_board_compat,
MACHINE_END

59
arch/arm/mach-at91/at91sam9260.c
View File

@ -1,59 +0,0 @@
/*
* arch/arm/mach-at91/at91sam9260.c
*
* Copyright (C) 2006 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9260 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9xe_map_io(void)
{
unsigned long sram_size;
switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
case AT91_CIDR_SRAMSIZ_32K:
sram_size = 2 * SZ_16K;
break;
case AT91_CIDR_SRAMSIZ_16K:
default:
sram_size = SZ_16K;
}
at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
}
static void __init at91sam9260_map_io(void)
{
if (cpu_is_at91sam9xe())
at91sam9xe_map_io();
else if (cpu_is_at91sam9g20())
at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
else
at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
}
static void __init at91sam9260_initialize(void)
{
arm_pm_idle = at91sam9_idle;
}
AT91_SOC_START(at91sam9260)
.map_io = at91sam9260_map_io,
.init = at91sam9260_initialize,
AT91_SOC_END

40
arch/arm/mach-at91/at91sam9261.c
View File

@ -1,40 +0,0 @@
/*
* arch/arm/mach-at91/at91sam9261.c
*
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9261 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9261_map_io(void)
{
if (cpu_is_at91sam9g10())
at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
else
at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
}
static void __init at91sam9261_initialize(void)
{
arm_pm_idle = at91sam9_idle;
}
AT91_SOC_START(at91sam9261)
.map_io = at91sam9261_map_io,
.init = at91sam9261_initialize,
AT91_SOC_END

37
arch/arm/mach-at91/at91sam9263.c
View File

@ -1,37 +0,0 @@
/*
* arch/arm/mach-at91/at91sam9263.c
*
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9263_map_io(void)
{
at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
}
static void __init at91sam9263_initialize(void)
{
arm_pm_idle = at91sam9_idle;
}
AT91_SOC_START(at91sam9263)
.map_io = at91sam9263_map_io,
.init = at91sam9263_initialize,
AT91_SOC_END

36
arch/arm/mach-at91/at91sam9g45.c
View File

@ -1,36 +0,0 @@
/*
* Chip-specific setup code for the AT91SAM9G45 family
*
* Copyright (C) 2009 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9G45 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9g45_map_io(void)
{
at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
}
static void __init at91sam9g45_initialize(void)
{
arm_pm_idle = at91sam9_idle;
}
AT91_SOC_START(at91sam9g45)
.map_io = at91sam9g45_map_io,
.init = at91sam9g45_initialize,
AT91_SOC_END

26
arch/arm/mach-at91/at91sam9n12.c
View File

@ -1,26 +0,0 @@
/*
* SoC specific setup code for the AT91SAM9N12
*
* Copyright (C) 2012 Atmel Corporation.
*
* Licensed under GPLv2 or later.
*/
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9n12_map_io(void)
{
at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
}
AT91_SOC_START(at91sam9n12)
.map_io = at91sam9n12_map_io,
AT91_SOC_END

49
arch/arm/mach-at91/at91sam9rl.c
View File

@ -1,49 +0,0 @@
/*
* arch/arm/mach-at91/at91sam9rl.c
*
* Copyright (C) 2005 SAN People
* Copyright (C) 2007 Atmel Corporation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9RL processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9rl_map_io(void)
{
unsigned long sram_size;
switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
case AT91_CIDR_SRAMSIZ_32K:
sram_size = 2 * SZ_16K;
break;
case AT91_CIDR_SRAMSIZ_16K:
default:
sram_size = SZ_16K;
}
/* Map SRAM */
at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
}
static void __init at91sam9rl_initialize(void)
{
arm_pm_idle = at91sam9_idle;
}
AT91_SOC_START(at91sam9rl)
.map_io = at91sam9rl_map_io,
.init = at91sam9rl_initialize,
AT91_SOC_END

26
arch/arm/mach-at91/at91sam9x5.c
View File

@ -1,26 +0,0 @@
/*
* Chip-specific setup code for the AT91SAM9x5 family
*
* Copyright (C) 2010-2012 Atmel Corporation.
*
* Licensed under GPLv2 or later.
*/
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9x5_map_io(void)
{
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
}
AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io,
AT91_SOC_END

43
arch/arm/mach-at91/board-dt-rm9200.c
View File

@ -1,43 +0,0 @@
/*
* Setup code for AT91RM9200 Evaluation Kits with Device Tree support
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
* 2012 Joachim Eastwood <manabian@gmail.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "generic.h"
static void __init at91rm9200_dt_timer_init(void)
{
of_clk_init(NULL);
at91rm9200_timer_init();
}
static const char *at91rm9200_dt_board_compat[] __initdata = {
"atmel,at91rm9200",
NULL
};
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
.init_time = at91rm9200_dt_timer_init,
.map_io = at91_map_io,
.init_early = at91_dt_initialize,
.dt_compat = at91rm9200_dt_board_compat,
MACHINE_END

36
arch/arm/mach-at91/board-dt-sam9.c
View File

@ -1,36 +0,0 @@
/*
* Setup code for AT91SAM Evaluation Kits with Device Tree support
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/clk-provider.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "generic.h"
static const char *at91_dt_board_compat[] __initdata = {
"atmel,at91sam9",
NULL
};
DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
/* Maintainer: Atmel */
.map_io = at91_map_io,
.init_early = at91_dt_initialize,
.dt_compat = at91_dt_board_compat,
MACHINE_END

20
arch/arm/mach-at91/generic.h
View File

@ -17,18 +17,28 @@
/* Map io */
extern void __init at91_map_io(void);
extern void __init at91_alt_map_io(void);
extern void __init at91_init_sram(int bank, unsigned long base,
unsigned int length);
/* Processors */
extern void __init at91_dt_initialize(void);
/* Timer */
extern void at91rm9200_timer_init(void);
/* idle */
extern void at91rm9200_idle(void);
extern void at91sam9_idle(void);
/* Matrix */
extern void at91_ioremap_matrix(u32 base_addr);
#ifdef CONFIG_PM
extern void __init at91rm9200_pm_init(void);
extern void __init at91sam9260_pm_init(void);
extern void __init at91sam9g45_pm_init(void);
extern void __init at91sam9x5_pm_init(void);
#else
void __init at91rm9200_pm_init(void) { }
void __init at91sam9260_pm_init(void) { }
void __init at91sam9g45_pm_init(void) { }
void __init at91sam9x5_pm_init(void) { }
#endif
#endif /* _AT91_GENERIC_H */

52
arch/arm/mach-at91/include/mach/cpu.h
View File

@ -152,69 +152,45 @@ static inline int at91_soc_is_detected(void)
#define cpu_is_at91rm9200_pqfp() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9260
#ifdef CONFIG_SOC_AT91SAM9
#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#define cpu_is_at91sam9g20() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9261
#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
#else
#define cpu_is_at91sam9261() (0)
#define cpu_is_at91sam9g10() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9263
#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
#else
#define cpu_is_at91sam9263() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9RL
#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
#else
#define cpu_is_at91sam9rl() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9G45
#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
#else
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
#define cpu_is_at91sam9m10() (0)
#define cpu_is_at91sam9g46() (0)
#define cpu_is_at91sam9m11() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9X5
#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#define cpu_is_at91sam9g20() (0)
#define cpu_is_at91sam9261() (0)
#define cpu_is_at91sam9g10() (0)
#define cpu_is_at91sam9263() (0)
#define cpu_is_at91sam9rl() (0)
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
#define cpu_is_at91sam9m10() (0)
#define cpu_is_at91sam9g46() (0)
#define cpu_is_at91sam9m11() (0)
#define cpu_is_at91sam9x5() (0)
#define cpu_is_at91sam9g15() (0)
#define cpu_is_at91sam9g35() (0)
#define cpu_is_at91sam9x35() (0)
#define cpu_is_at91sam9g25() (0)
#define cpu_is_at91sam9x25() (0)
#endif
#ifdef CONFIG_SOC_AT91SAM9N12
#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
#else
#define cpu_is_at91sam9n12() (0)
#endif

27
arch/arm/mach-at91/include/mach/system_rev.h
View File

@ -1,27 +0,0 @@
/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2 only
*/
#ifndef __ARCH_SYSTEM_REV_H__
#define __ARCH_SYSTEM_REV_H__
#include <asm/system_info.h>
/*
* board revision encoding
* mach specific
* the 16-31 bit are reserved for at91 generic information
*
* bit 31:
* 0 => nand 8 bit
* 1 => nand 16 bit
*/
#define BOARD_HAVE_NAND_16BIT (1 << 31)
static inline int board_have_nand_16bit(void)
{
return (system_rev & BOARD_HAVE_NAND_16BIT) ? 1 : 0;
}
#endif /* __ARCH_SYSTEM_REV_H__ */

158
arch/arm/mach-at91/pm.c
View File

@ -14,9 +14,13 @@
#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/genalloc.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk/at91_pmc.h>
@ -32,7 +36,13 @@
#include "generic.h"
#include "pm.h"
static struct {
unsigned long uhp_udp_mask;
int memctrl;
} at91_pm_data;
static void (*at91_pm_standby)(void);
void __iomem *at91_ramc_base[2];
static int at91_pm_valid_state(suspend_state_t state)
{
@ -71,18 +81,10 @@ static int at91_pm_verify_clocks(void)
scsr = at91_pmc_read(AT91_PMC_SCSR);
/* USB must not be using PLLB */
if (cpu_is_at91rm9200()) {
if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
return 0;
}
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
|| cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
return 0;
}
}
/* PCK0..PCK3 must be disabled, or configured to use clk32k */
for (i = 0; i < 4; i++) {
@ -149,18 +151,13 @@ static int at91_pm_enter(suspend_state_t state)
* turning off the main oscillator; reverse on wakeup.
*/
if (slow_clock) {
int memctrl = AT91_MEMCTRL_SDRAMC;
if (cpu_is_at91rm9200())
memctrl = AT91_MEMCTRL_MC;
else if (cpu_is_at91sam9g45())
memctrl = AT91_MEMCTRL_DDRSDR;
#ifdef CONFIG_AT91_SLOW_CLOCK
/* copy slow_clock handler to SRAM, and call it */
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
#endif
slow_clock(at91_pmc_base, at91_ramc_base[0],
at91_ramc_base[1], memctrl);
at91_ramc_base[1],
at91_pm_data.memctrl);
break;
} else {
pr_info("AT91: PM - no slow clock mode enabled ...\n");
@ -229,23 +226,134 @@ void at91_pm_set_standby(void (*at91_standby)(void))
}
}
static int __init at91_pm_init(void)
static struct of_device_id ramc_ids[] = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
{ /*sentinel*/ }
};
static void at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
const void *standby = NULL;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
at91_ramc_base[idx] = of_iomap(np, 0);
if (!at91_ramc_base[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
if (!standby)
standby = of_id->data;
idx++;
}
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
if (!standby) {
pr_warn("ramc no standby function available\n");
return;
}
at91_pm_set_standby(standby);
}
#ifdef CONFIG_AT91_SLOW_CLOCK
static void __init at91_pm_sram_init(void)
{
struct gen_pool *sram_pool;
phys_addr_t sram_pbase;
unsigned long sram_base;
struct device_node *node;
struct platform_device *pdev;
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
if (!node) {
pr_warn("%s: failed to find sram node!\n", __func__);
return;
}
pdev = of_find_device_by_node(node);
if (!pdev) {
pr_warn("%s: failed to find sram device!\n", __func__);
goto put_node;
}
sram_pool = dev_get_gen_pool(&pdev->dev);
if (!sram_pool) {
pr_warn("%s: sram pool unavailable!\n", __func__);
goto put_node;
}
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
if (!sram_base) {
pr_warn("%s: unable to alloc ocram!\n", __func__);
goto put_node;
}
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
put_node:
of_node_put(node);
}
#endif
static void __init at91_pm_init(void)
{
#ifdef CONFIG_AT91_SLOW_CLOCK
slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
at91_pm_sram_init();
#endif
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
if (cpu_is_at91rm9200())
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
suspend_set_ops(&at91_pm_ops);
return 0;
}
arch_initcall(at91_pm_init);
void __init at91rm9200_pm_init(void)
{
at91_dt_ramc();
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
*/
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_MC;
at91_pm_init();
}
void __init at91sam9260_pm_init(void)
{
at91_dt_ramc();
at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
return at91_pm_init();
}
void __init at91sam9g45_pm_init(void)
{
at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
return at91_pm_init();
}
void __init at91sam9x5_pm_init(void)
{
at91_dt_ramc();
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
return at91_pm_init();
}

9
arch/arm/mach-at91/pm_slowclock.S
View File

@ -17,15 +17,6 @@
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
#ifdef CONFIG_SOC_AT91SAM9263
/*
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
* handle those cases both here and in the Suspend-To-RAM support.
*/
#warning Assuming EB1 SDRAM controller is *NOT* used
#endif
/*
* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
* clock during suspend by adjusting its prescalar and divisor.

46
arch/arm/mach-at91/board-dt-sama5.c → arch/arm/mach-at91/sama5.c
View File

@ -1,5 +1,5 @@
/*
* Setup code for SAMA5 Evaluation Kits with Device Tree support
* Setup code for SAMA5
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
@ -19,6 +19,8 @@
#include <linux/clk-provider.h>
#include <linux/phy.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
@ -47,6 +49,7 @@ static void __init sama5_dt_device_init(void)
}
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
at91sam9x5_pm_init();
}
static const char *sama5_dt_board_compat[] __initconst = {
@ -54,23 +57,54 @@ static const char *sama5_dt_board_compat[] __initconst = {
NULL
};
DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
DT_MACHINE_START(sama5_dt, "Atmel SAMA5")
/* Maintainer: Atmel */
.map_io = at91_map_io,
.init_early = at91_dt_initialize,
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_dt_board_compat,
MACHINE_END
static struct map_desc at91_io_desc[] __initdata = {
{
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
.pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
.length = SZ_512,
.type = MT_DEVICE,
},
{
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
.pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
.length = SZ_512,
.type = MT_DEVICE,
},
{ /* On sama5d4, we use USART3 as serial console */
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
.pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
.length = SZ_256,
.type = MT_DEVICE,
},
{ /* A bunch of peripheral with fine grained IO space */
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
.pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
.length = SZ_2K,
.type = MT_DEVICE,
},
};
static void __init sama5_alt_map_io(void)
{
at91_alt_map_io();
iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
}
static const char *sama5_alt_dt_board_compat[] __initconst = {
"atmel,sama5d4",
NULL
};
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5")
/* Maintainer: Atmel */
.map_io = at91_alt_map_io,
.init_early = at91_dt_initialize,
.map_io = sama5_alt_map_io,
.init_machine = sama5_dt_device_init,
.dt_compat = sama5_alt_dt_board_compat,
.l2c_aux_mask = ~0UL,

35
arch/arm/mach-at91/sama5d3.c
View File

@ -1,35 +0,0 @@
/*
* Chip-specific setup code for the SAMA5D3 family
*
* Copyright (C) 2013 Atmel,
* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d3.h>
#include <mach/cpu.h>
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
static void __init sama5d3_map_io(void)
{
at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
}
AT91_SOC_START(sama5d3)
.map_io = sama5d3_map_io,
AT91_SOC_END

64
arch/arm/mach-at91/sama5d4.c
View File

@ -1,64 +0,0 @@
/*
* Chip-specific setup code for the SAMA5D4 family
*
* Copyright (C) 2013 Atmel Corporation,
* Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/sama5d4.h>
#include <mach/cpu.h>
#include <mach/hardware.h>
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
* Processor initialization
* -------------------------------------------------------------------- */
static struct map_desc at91_io_desc[] __initdata = {
{
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
.pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
.length = SZ_512,
.type = MT_DEVICE,
},
{
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
.pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
.length = SZ_512,
.type = MT_DEVICE,
},
{ /* On sama5d4, we use USART3 as serial console */
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
.pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
.length = SZ_256,
.type = MT_DEVICE,
},
{ /* A bunch of peripheral with fine grained IO space */
.virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
.pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
.length = SZ_2K,
.type = MT_DEVICE,
},
};
static void __init sama5d4_map_io(void)
{
iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
}
AT91_SOC_START(sama5d4)
.map_io = sama5d4_map_io,
AT91_SOC_END

97
arch/arm/mach-at91/setup.c
View File

@ -22,38 +22,12 @@
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include "soc.h"
#include "generic.h"
#include "pm.h"
struct at91_init_soc __initdata at91_boot_soc;
struct at91_socinfo at91_soc_initdata;
EXPORT_SYMBOL(at91_soc_initdata);
void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);
static struct map_desc sram_desc[2] __initdata;
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
{
struct map_desc *desc = &sram_desc[bank];
desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
if (bank > 0)
desc->virtual -= sram_desc[bank - 1].length;
desc->pfn = __phys_to_pfn(base);
desc->length = length;
desc->type = MT_MEMORY_RWX_NONCACHED;
pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
base, length, desc->virtual);
iotable_init(desc, 1);
}
static struct map_desc at91_io_desc __initdata __maybe_unused = {
.virtual = (unsigned long)AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
@ -80,61 +54,51 @@ static void __init soc_detect(u32 dbgu_base)
at91_soc_initdata.type = AT91_SOC_RM9200;
if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
at91_boot_soc = at91rm9200_soc;
break;
case ARCH_ID_AT91SAM9260:
at91_soc_initdata.type = AT91_SOC_SAM9260;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9260_soc;
break;
case ARCH_ID_AT91SAM9261:
at91_soc_initdata.type = AT91_SOC_SAM9261;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9261_soc;
break;
case ARCH_ID_AT91SAM9263:
at91_soc_initdata.type = AT91_SOC_SAM9263;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9263_soc;
break;
case ARCH_ID_AT91SAM9G20:
at91_soc_initdata.type = AT91_SOC_SAM9G20;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9260_soc;
break;
case ARCH_ID_AT91SAM9G45:
at91_soc_initdata.type = AT91_SOC_SAM9G45;
if (cidr == ARCH_ID_AT91SAM9G45ES)
at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
at91_boot_soc = at91sam9g45_soc;
break;
case ARCH_ID_AT91SAM9RL64:
at91_soc_initdata.type = AT91_SOC_SAM9RL;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9rl_soc;
break;
case ARCH_ID_AT91SAM9X5:
at91_soc_initdata.type = AT91_SOC_SAM9X5;
at91_boot_soc = at91sam9x5_soc;
break;
case ARCH_ID_AT91SAM9N12:
at91_soc_initdata.type = AT91_SOC_SAM9N12;
at91_boot_soc = at91sam9n12_soc;
break;
case ARCH_ID_SAMA5:
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
at91_boot_soc = sama5d3_soc;
}
break;
}
@ -143,13 +107,11 @@ static void __init soc_detect(u32 dbgu_base)
if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
at91_soc_initdata.type = AT91_SOC_SAM9G10;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
at91_boot_soc = at91sam9261_soc;
}
/* at91sam9xe */
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
at91_soc_initdata.type = AT91_SOC_SAM9260;
at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
at91_boot_soc = at91sam9260_soc;
}
if (!at91_soc_is_detected())
@ -229,10 +191,8 @@ static void __init alt_soc_detect(u32 dbgu_base)
at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
at91_soc_initdata.type = AT91_SOC_SAMA5D3;
at91_boot_soc = sama5d3_soc;
} else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
at91_soc_initdata.type = AT91_SOC_SAMA5D4;
at91_boot_soc = sama5d4_soc;
}
break;
}
@ -338,12 +298,6 @@ void __init at91_map_io(void)
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
pr_info("Detected soc subtype: %s\n",
at91_get_soc_subtype(&at91_soc_initdata));
if (!at91_soc_is_enabled())
panic(pr_fmt("Soc not enabled"));
if (at91_boot_soc.map_io)
at91_boot_soc.map_io();
}
void __init at91_alt_map_io(void)
@ -363,12 +317,6 @@ void __init at91_alt_map_io(void)
if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
pr_info("AT91: Detected soc subtype: %s\n",
at91_get_soc_subtype(&at91_soc_initdata));
if (!at91_soc_is_enabled())
panic("AT91: Soc not enabled");
if (at91_boot_soc.map_io)
at91_boot_soc.map_io();
}
void __iomem *at91_matrix_base;
@ -380,48 +328,3 @@ void __init at91_ioremap_matrix(u32 base_addr)
if (!at91_matrix_base)
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
}
static struct of_device_id ramc_ids[] = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
{ /*sentinel*/ }
};
static void at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
const void *standby = NULL;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
at91_ramc_base[idx] = of_iomap(np, 0);
if (!at91_ramc_base[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
if (!standby)
standby = of_id->data;
idx++;
}
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
if (!standby) {
pr_warn("ramc no standby function available\n");
return;
}
at91_pm_set_standby(standby);
}
void __init at91_dt_initialize(void)
{
at91_dt_ramc();
if (at91_boot_soc.init)
at91_boot_soc.init();
}

77
arch/arm/mach-at91/soc.h
View File

@ -1,77 +0,0 @@
/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
struct at91_init_soc {
int builtin;
void (*map_io)(void);
void (*init)(void);
};
extern struct at91_init_soc at91_boot_soc;
extern struct at91_init_soc at91rm9200_soc;
extern struct at91_init_soc at91sam9260_soc;
extern struct at91_init_soc at91sam9261_soc;
extern struct at91_init_soc at91sam9263_soc;
extern struct at91_init_soc at91sam9g45_soc;
extern struct at91_init_soc at91sam9rl_soc;
extern struct at91_init_soc at91sam9x5_soc;
extern struct at91_init_soc at91sam9n12_soc;
extern struct at91_init_soc sama5d3_soc;
extern struct at91_init_soc sama5d4_soc;
#define AT91_SOC_START(_name) \
struct at91_init_soc __initdata _name##_soc \
__used \
= { \
.builtin = 1, \
#define AT91_SOC_END \
};
static inline int at91_soc_is_enabled(void)
{
return at91_boot_soc.builtin;
}
#if !defined(CONFIG_SOC_AT91RM9200)
#define at91rm9200_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9260)
#define at91sam9260_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9261)
#define at91sam9261_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9263)
#define at91sam9263_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9G45)
#define at91sam9g45_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9RL)
#define at91sam9rl_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9X5)
#define at91sam9x5_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_AT91SAM9N12)
#define at91sam9n12_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_SAMA5D3)
#define sama5d3_soc at91_boot_soc
#endif
#if !defined(CONFIG_SOC_SAMA5D4)
#define sama5d4_soc at91_boot_soc
#endif

85
arch/arm/mach-bcm/platsmp-brcmstb.c
View File

@ -17,6 +17,7 @@
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/printk.h>
@ -94,10 +95,35 @@ static u32 pwr_ctrl_rd(u32 cpu)
return readl_relaxed(base);
}
static void pwr_ctrl_wr(u32 cpu, u32 val)
static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask)
{
void __iomem *base = pwr_ctrl_get_base(cpu);
writel(val, base);
writel((readl(base) & mask) | val, base);
}
static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask)
{
void __iomem *base = pwr_ctrl_get_base(cpu);
writel((readl(base) & mask) & ~val, base);
}
#define POLL_TMOUT_MS 500
static int pwr_ctrl_wait_tmout(unsigned int cpu, u32 set, u32 mask)
{
const unsigned long timeo = jiffies + msecs_to_jiffies(POLL_TMOUT_MS);
u32 tmp;
do {
tmp = pwr_ctrl_rd(cpu) & mask;
if (!set == !tmp)
return 0;
} while (time_before(jiffies, timeo));
tmp = pwr_ctrl_rd(cpu) & mask;
if (!set == !tmp)
return 0;
return -ETIMEDOUT;
}
static void cpu_rst_cfg_set(u32 cpu, int set)
@ -139,15 +165,22 @@ static void brcmstb_cpu_power_on(u32 cpu)
* The secondary cores power was cut, so we must go through
* power-on initialization.
*/
u32 tmp;
pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, 0xffffff00);
pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
pwr_ctrl_set(cpu, ZONE_RESERVED_1_MASK, -1);
/* Request zone power up */
pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
pwr_ctrl_set(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
/* Wait for the power up FSM to complete */
do {
tmp = pwr_ctrl_rd(cpu);
} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_MEM_PWR_STATE_MASK))
panic("ZONE_MEM_PWR_STATE_MASK set timeout");
pwr_ctrl_set(cpu, ZONE_MAN_CLKEN_MASK, -1);
if (pwr_ctrl_wait_tmout(cpu, 1, ZONE_DPG_PWR_STATE_MASK))
panic("ZONE_DPG_PWR_STATE_MASK set timeout");
pwr_ctrl_clr(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
pwr_ctrl_set(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
}
static int brcmstb_cpu_get_power_state(u32 cpu)
@ -174,25 +207,33 @@ static void brcmstb_cpu_die(u32 cpu)
static int brcmstb_cpu_kill(u32 cpu)
{
u32 tmp;
/*
* Ordinarily, the hardware forbids power-down of CPU0 (which is good
* because it is the boot CPU), but this is not true when using BPCM
* manual mode. Consequently, we must avoid turning off CPU0 here to
* ensure that TI2C master reset will work.
*/
if (cpu == 0) {
pr_warn("SMP: refusing to power off CPU0\n");
return 1;
}
while (per_cpu_sw_state_rd(cpu))
;
/* Program zone reset */
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
ZONE_PWR_DN_REQ_MASK);
pwr_ctrl_set(cpu, ZONE_MANUAL_CONTROL_MASK, -1);
pwr_ctrl_clr(cpu, ZONE_MAN_RESET_CNTL_MASK, -1);
pwr_ctrl_clr(cpu, ZONE_MAN_CLKEN_MASK, -1);
pwr_ctrl_set(cpu, ZONE_MAN_ISO_CNTL_MASK, -1);
pwr_ctrl_clr(cpu, ZONE_MAN_MEM_PWR_MASK, -1);
/* Verify zone reset */
tmp = pwr_ctrl_rd(cpu);
if (!(tmp & ZONE_RESET_STATE_MASK))
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
__func__, cpu);
if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_MEM_PWR_STATE_MASK))
panic("ZONE_MEM_PWR_STATE_MASK clear timeout");
/* Wait for power down */
do {
tmp = pwr_ctrl_rd(cpu);
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
pwr_ctrl_clr(cpu, ZONE_RESERVED_1_MASK, -1);
if (pwr_ctrl_wait_tmout(cpu, 0, ZONE_DPG_PWR_STATE_MASK))
panic("ZONE_DPG_PWR_STATE_MASK clear timeout");
/* Flush pipeline before resetting CPU */
mb();

7
arch/arm/mach-digicolor/Kconfig Normal file
View File

@ -0,0 +1,7 @@
config ARCH_DIGICOLOR
bool "Conexant Digicolor SoC Support"
depends on ARCH_MULTI_V7
select CLKSRC_MMIO
select DIGICOLOR_TIMER
select GENERIC_IRQ_CHIP
select MFD_SYSCON

1
arch/arm/mach-digicolor/Makefile Normal file
View File

@ -0,0 +1 @@
obj-$(CONFIG_ARCH_DIGICOLOR) += digicolor.o

18
arch/arm/mach-digicolor/digicolor.c Normal file
View File

@ -0,0 +1,18 @@
/*
* Support for Conexant Digicolor SoCs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/mach/arch.h>
static const char *digicolor_dt_compat[] __initconst = {
"cnxt,cx92755",
NULL,
};
DT_MACHINE_START(DIGICOLOR, "Conexant Digicolor (Flattened Device Tree)")
.dt_compat = digicolor_dt_compat,
MACHINE_END

1
arch/arm/mach-exynos/exynos.c
View File

@ -247,6 +247,7 @@ static void __init exynos_reserve(void)
"samsung,mfc-v5",
"samsung,mfc-v6",
"samsung,mfc-v7",
"samsung,mfc-v8",
};
for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)

3
arch/arm/mach-exynos/regs-pmu.h
View File

@ -160,12 +160,14 @@
#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3)
#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
#define S5P_PAD_RET_MMC2_OPTION 0x30c8
#define S5P_PAD_RET_GPIO_OPTION 0x3108
#define S5P_PAD_RET_UART_OPTION 0x3128
#define S5P_PAD_RET_MMCA_OPTION 0x3148
#define S5P_PAD_RET_MMCB_OPTION 0x3168
#define S5P_PAD_RET_EBIA_OPTION 0x3188
#define S5P_PAD_RET_EBIB_OPTION 0x31A8
#define S5P_PAD_RET_SPI_OPTION 0x31c8
#define S5P_PS_HOLD_CONTROL 0x330C
#define S5P_PS_HOLD_EN (1 << 31)
@ -326,6 +328,7 @@
(EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
#define EXYNOS3_ARM_COMMON_OPTION 0x2408
#define EXYNOS3_ARM_L2_OPTION 0x2608
#define EXYNOS3_TOP_PWR_OPTION 0x2C48
#define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8
#define EXYNOS3_XUSBXTI_DURATION 0x341C

77
arch/arm/mach-exynos/suspend.c
View File

@ -86,6 +86,12 @@ static unsigned int exynos_pmu_spare3;
static u32 exynos_irqwake_intmask = 0xffffffff;
static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
{ 73, BIT(1) }, /* RTC alarm */
{ 74, BIT(2) }, /* RTC tick */
{ /* sentinel */ },
};
static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
{ 76, BIT(1) }, /* RTC alarm */
{ 77, BIT(2) }, /* RTC tick */
@ -109,6 +115,19 @@ unsigned int exynos_release_ret_regs[] = {
REG_TABLE_END,
};
unsigned int exynos3250_release_ret_regs[] = {
S5P_PAD_RET_MAUDIO_OPTION,
S5P_PAD_RET_GPIO_OPTION,
S5P_PAD_RET_UART_OPTION,
S5P_PAD_RET_MMCA_OPTION,
S5P_PAD_RET_MMCB_OPTION,
S5P_PAD_RET_EBIA_OPTION,
S5P_PAD_RET_EBIB_OPTION,
S5P_PAD_RET_MMC2_OPTION,
S5P_PAD_RET_SPI_OPTION,
REG_TABLE_END,
};
unsigned int exynos5420_release_ret_regs[] = {
EXYNOS_PAD_RET_DRAM_OPTION,
EXYNOS_PAD_RET_MAUDIO_OPTION,
@ -168,6 +187,12 @@ static int exynos_cpu_suspend(unsigned long arg)
return exynos_cpu_do_idle();
}
static int exynos3250_cpu_suspend(unsigned long arg)
{
flush_cache_all();
return exynos_cpu_do_idle();
}
static int exynos5420_cpu_suspend(unsigned long arg)
{
/* MCPM works with HW CPU identifiers */
@ -225,6 +250,23 @@ static void exynos_pm_prepare(void)
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos3250_pm_prepare(void)
{
unsigned int tmp;
/* Set wake-up mask registers */
exynos_pm_set_wakeup_mask();
tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
exynos_pm_enter_sleep_mode();
/* ensure at least INFORM0 has the resume address */
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos5420_pm_prepare(void)
{
unsigned int tmp;
@ -339,6 +381,28 @@ static void exynos_pm_resume(void)
pmu_raw_writel(0x0, S5P_INFORM1);
}
static void exynos3250_pm_resume(void)
{
u32 cpuid = read_cpuid_part();
if (exynos_pm_central_resume())
goto early_wakeup;
/* For release retention */
exynos_pm_release_retention();
pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
if (call_firmware_op(resume) == -ENOSYS
&& cpuid == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_restore_register();
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
pmu_raw_writel(0x0, S5P_INFORM1);
}
static void exynos5420_prepare_pm_resume(void)
{
if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
@ -478,6 +542,16 @@ static const struct platform_suspend_ops exynos_suspend_ops = {
.valid = suspend_valid_only_mem,
};
static const struct exynos_pm_data exynos3250_pm_data = {
.wkup_irq = exynos3250_wkup_irq,
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
.release_ret_regs = exynos3250_release_ret_regs,
.pm_suspend = exynos_pm_suspend,
.pm_resume = exynos3250_pm_resume,
.pm_prepare = exynos3250_pm_prepare,
.cpu_suspend = exynos3250_cpu_suspend,
};
static const struct exynos_pm_data exynos4_pm_data = {
.wkup_irq = exynos4_wkup_irq,
.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
@ -511,6 +585,9 @@ static struct exynos_pm_data exynos5420_pm_data = {
static struct of_device_id exynos_pmu_of_device_ids[] = {
{
.compatible = "samsung,exynos3250-pmu",
.data = &exynos3250_pm_data,
}, {
.compatible = "samsung,exynos4210-pmu",
.data = &exynos4_pm_data,
}, {

8
arch/arm/mach-hisi/Kconfig
View File

@ -22,6 +22,14 @@ config ARCH_HI3xxx
help
Support for Hisilicon Hi36xx SoC family
config ARCH_HIP01
bool "Hisilicon HIP01 family" if ARCH_MULTI_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select ARM_GLOBAL_TIMER
help
Support for Hisilicon HIP01 SoC family
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family" if ARCH_MULTI_V7
select ARM_ERRATA_798181 if SMP

5
arch/arm/mach-hisi/core.h
View File

@ -12,9 +12,12 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
extern void hix5hd2_secondary_startup(void);
extern void hisi_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu);
extern struct smp_operations hip01_smp_ops;
extern void hip01_set_cpu(int cpu, bool enable);
extern void hip01_cpu_die(unsigned int cpu);
#endif

2
arch/arm/mach-hisi/headsmp.S
View File

@ -11,6 +11,6 @@
__CPUINIT
ENTRY(hix5hd2_secondary_startup)
ENTRY(hisi_secondary_startup)
bl v7_invalidate_l1
b secondary_startup

10
arch/arm/mach-hisi/hisilicon.c
View File

@ -72,3 +72,13 @@ static const char *hip04_compat[] __initconst = {
DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
.dt_compat = hip04_compat,
MACHINE_END
static const char *hip01_compat[] __initconst = {
"hisilicon,hip01",
"hisilicon,hip01-ca9x2",
NULL,
};
DT_MACHINE_START(HIP01, "Hisilicon HIP01 (Flattened Device Tree)")
.dt_compat = hip01_compat,
MACHINE_END

31
arch/arm/mach-hisi/hotplug.c
View File

@ -65,6 +65,9 @@
#define PMC0_CPU1_PMC_ENABLE (1 << 7)
#define PMC0_CPU1_POWERDOWN (1 << 3)
#define HIP01_PERI9 0x50
#define PERI9_CPU1_RESET (1 << 1)
enum {
HI3620_CTRL,
ERROR_CTRL,
@ -209,6 +212,34 @@ void hix5hd2_set_cpu(int cpu, bool enable)
}
}
void hip01_set_cpu(int cpu, bool enable)
{
unsigned int temp;
struct device_node *np;
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
if (np)
ctrl_base = of_iomap(np, 0);
else
BUG();
}
if (enable) {
/* reset on CPU1 */
temp = readl_relaxed(ctrl_base + HIP01_PERI9);
temp |= PERI9_CPU1_RESET;
writel_relaxed(temp, ctrl_base + HIP01_PERI9);
udelay(50);
/* unreset on CPU1 */
temp = readl_relaxed(ctrl_base + HIP01_PERI9);
temp &= ~PERI9_CPU1_RESET;
writel_relaxed(temp, ctrl_base + HIP01_PERI9);
}
}
static inline void cpu_enter_lowpower(void)
{
unsigned int v;

56
arch/arm/mach-hisi/platsmp.c
View File

@ -10,10 +10,12 @@
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/delay.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/mach/map.h>
#include "core.h"
@ -96,7 +98,7 @@ struct smp_operations hi3xxx_smp_ops __initdata = {
#endif
};
static void __init hix5hd2_smp_prepare_cpus(unsigned int max_cpus)
static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
{
hisi_enable_scu_a9();
}
@ -116,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t jumpaddr;
jumpaddr = virt_to_phys(hix5hd2_secondary_startup);
jumpaddr = virt_to_phys(hisi_secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
@ -125,12 +127,60 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct smp_operations hix5hd2_smp_ops __initdata = {
.smp_prepare_cpus = hix5hd2_smp_prepare_cpus,
.smp_prepare_cpus = hisi_common_smp_prepare_cpus,
.smp_boot_secondary = hix5hd2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = hix5hd2_cpu_die,
#endif
};
#define SC_SCTL_REMAP_CLR 0x00000100
#define HIP01_BOOT_ADDRESS 0x80000000
#define REG_SC_CTRL 0x000
void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
{
void __iomem *virt;
virt = phys_to_virt(start_addr);
writel_relaxed(0xe51ff004, virt);
writel_relaxed(jump_addr, virt + 4);
}
static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
phys_addr_t jumpaddr;
unsigned int remap_reg_value = 0;
struct device_node *node;
jumpaddr = virt_to_phys(hisi_secondary_startup);
hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
if (WARN_ON(!node))
return -1;
ctrl_base = of_iomap(node, 0);
/* set the secondary core boot from DDR */
remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
barrier();
remap_reg_value |= SC_SCTL_REMAP_CLR;
barrier();
writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
hip01_set_cpu(cpu, true);
return 0;
}
struct smp_operations hip01_smp_ops __initdata = {
.smp_prepare_cpus = hisi_common_smp_prepare_cpus,
.smp_boot_secondary = hip01_boot_secondary,
};
CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);

3
arch/arm/mach-imx/Makefile
View File

@ -32,8 +32,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
# i.MX6SX reuses i.MX6Q cpuidle driver
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
endif
ifdef CONFIG_SND_IMX_SOC

21
arch/arm/mach-imx/clk-gate2.c
View File

@ -96,15 +96,30 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
if (gate->share_count)
return !!__clk_get_enable_count(hw->clk);
else
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
}
static void clk_gate2_disable_unused(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
unsigned long flags = 0;
u32 reg;
spin_lock_irqsave(gate->lock, flags);
if (!gate->share_count || *gate->share_count == 0) {
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
}
spin_unlock_irqrestore(gate->lock, flags);
}
static struct clk_ops clk_gate2_ops = {
.enable = clk_gate2_enable,
.disable = clk_gate2_disable,
.disable_unused = clk_gate2_disable_unused,
.is_enabled = clk_gate2_is_enabled,
};

2
arch/arm/mach-imx/clk-imx6q.c
View File

@ -386,7 +386,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ipg", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);

10
arch/arm/mach-imx/clk-pllv3.c
View File

@ -31,6 +31,7 @@
* @base: base address of PLL registers
* @powerup_set: set POWER bit to power up the PLL
* @div_mask: mask of divider bits
* @div_shift: shift of divider bits
*
* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
* is actually a multiplier, and always sits at bit 0.
@ -40,6 +41,7 @@ struct clk_pllv3 {
void __iomem *base;
bool powerup_set;
u32 div_mask;
u32 div_shift;
};
#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 div = readl_relaxed(pll->base) & pll->div_mask;
u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}
@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;
val = readl_relaxed(pll->base);
val &= ~pll->div_mask;
val |= div;
val &= ~(pll->div_mask << pll->div_shift);
val |= (div << pll->div_shift);
writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll);
@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
case IMX_PLLV3_SYS:
ops = &clk_pllv3_sys_ops;
break;
case IMX_PLLV3_USB_VF610:
pll->div_shift = 1;
case IMX_PLLV3_USB:
ops = &clk_pllv3_ops;
pll->powerup_set = true;

8
arch/arm/mach-imx/clk-vf610.c
View File

@ -172,11 +172,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);
clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);
clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);
clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2);
clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
@ -267,6 +267,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9));
clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10));
clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
@ -380,6 +382,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);

1
arch/arm/mach-imx/clk.h
View File

@ -20,6 +20,7 @@ enum imx_pllv3_type {
IMX_PLLV3_GENERIC,
IMX_PLLV3_SYS,
IMX_PLLV3_USB,
IMX_PLLV3_USB_VF610,
IMX_PLLV3_AV,
IMX_PLLV3_ENET,
};

4
arch/arm/mach-imx/common.h
View File

@ -70,6 +70,10 @@ void imx_set_soc_revision(unsigned int rev);
unsigned int imx_get_soc_revision(void);
void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */

105
arch/arm/mach-imx/cpuidle-imx6sx.c Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/module.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include "common.h"
#include "cpuidle.h"
static int imx6sx_idle_finish(unsigned long val)
{
cpu_do_idle();
return 0;
}
static int imx6sx_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
imx6q_set_lpm(WAIT_UNCLOCKED);
switch (index) {
case 1:
cpu_do_idle();
break;
case 2:
imx6_enable_rbc(true);
imx_gpc_set_arm_power_in_lpm(true);
imx_set_cpu_jump(0, v7_cpu_resume);
/* Need to notify there is a cpu pm operation. */
cpu_pm_enter();
cpu_cluster_pm_enter();
cpu_suspend(0, imx6sx_idle_finish);
cpu_cluster_pm_exit();
cpu_pm_exit();
imx_gpc_set_arm_power_in_lpm(false);
imx6_enable_rbc(false);
break;
default:
break;
}
imx6q_set_lpm(WAIT_CLOCKED);
return index;
}
static struct cpuidle_driver imx6sx_cpuidle_driver = {
.name = "imx6sx_cpuidle",
.owner = THIS_MODULE,
.states = {
/* WFI */
ARM_CPUIDLE_WFI_STATE,
/* WAIT */
{
.exit_latency = 50,
.target_residency = 75,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sx_enter_wait,
.name = "WAIT",
.desc = "Clock off",
},
/* WAIT + ARM power off */
{
/*
* ARM gating 31us * 5 + RBC clear 65us
* and some margin for SW execution, here set it
* to 300us.
*/
.exit_latency = 300,
.target_residency = 500,
.enter = imx6sx_enter_wait,
.name = "LOW-POWER-IDLE",
.desc = "ARM power off",
},
},
.state_count = 3,
.safe_state_index = 0,
};
int __init imx6sx_cpuidle_init(void)
{
imx6_enable_rbc(false);
/*
* set ARM power up/down timing to the fastest,
* sw2iso and sw can be set to one 32K cycle = 31us
* except for power up sw2iso which need to be
* larger than LDO ramp up time.
*/
imx_gpc_set_arm_power_up_timing(2, 1);
imx_gpc_set_arm_power_down_timing(1, 1);
return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
}

5
arch/arm/mach-imx/cpuidle.h
View File

@ -14,6 +14,7 @@
extern int imx5_cpuidle_init(void);
extern int imx6q_cpuidle_init(void);
extern int imx6sl_cpuidle_init(void);
extern int imx6sx_cpuidle_init(void);
#else
static inline int imx5_cpuidle_init(void)
{
@ -27,4 +28,8 @@ static inline int imx6sl_cpuidle_init(void)
{
return 0;
}
static inline int imx6sx_cpuidle_init(void)
{
return 0;
}
#endif

25
arch/arm/mach-imx/gpc.c
View File

@ -20,6 +20,10 @@
#define GPC_IMR1 0x008
#define GPC_PGC_CPU_PDN 0x2a0
#define GPC_PGC_CPU_PUPSCR 0x2a4
#define GPC_PGC_CPU_PDNSCR 0x2a8
#define GPC_PGC_SW2ISO_SHIFT 0x8
#define GPC_PGC_SW_SHIFT 0x0
#define IMR_NUM 4
@ -27,6 +31,23 @@ static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
{
writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
}
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
{
writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
}
void imx_gpc_set_arm_power_in_lpm(bool power_off)
{
writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
}
void imx_gpc_pre_suspend(bool arm_power_off)
{
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
@ -34,7 +55,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
/* Tell GPC to power off ARM core when suspend */
if (arm_power_off)
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
imx_gpc_set_arm_power_in_lpm(arm_power_off);
for (i = 0; i < IMR_NUM; i++) {
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
@ -48,7 +69,7 @@ void imx_gpc_post_resume(void)
int i;
/* Keep ARM core powered on for other low-power modes */
writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
imx_gpc_set_arm_power_in_lpm(false);
for (i = 0; i < IMR_NUM; i++)
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);

2
arch/arm/mach-imx/mach-imx6q.c
View File

@ -329,7 +329,7 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
if (dev_pm_opp_disable(cpu_dev, 852000000))
pr_warn("failed to disable 852 MHz OPP\n");
}
iounmap(base);
put_node:
of_node_put(np);
}

2
arch/arm/mach-imx/mach-imx6sx.c
View File

@ -90,7 +90,7 @@ static void __init imx6sx_init_irq(void)
static void __init imx6sx_init_late(void)
{
imx6q_cpuidle_init();
imx6sx_cpuidle_init();
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);

5
arch/arm/mach-imx/mach-vf610.c
View File

@ -13,11 +13,14 @@
#include <asm/hardware/cache-l2x0.h>
static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf500",
"fsl,vf510",
"fsl,vf600",
"fsl,vf610",
NULL,
};
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.dt_compat = vf610_dt_compat,

7
arch/arm/mach-imx/pm-imx6.c
View File

@ -205,7 +205,7 @@ void imx6q_set_int_mem_clk_lpm(bool enable)
writel_relaxed(val, ccm_base + CGPR);
}
static void imx6q_enable_rbc(bool enable)
void imx6_enable_rbc(bool enable)
{
u32 val;
@ -359,17 +359,16 @@ static int imx6q_pm_enter(suspend_state_t state)
* RBC setting, so we do NOT need to do that here.
*/
if (!imx6_suspend_in_ocram_fn)
imx6q_enable_rbc(true);
imx6_enable_rbc(true);
imx_gpc_pre_suspend(true);
imx_anatop_pre_suspend();
imx_set_cpu_jump(0, v7_cpu_resume);
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
if (cpu_is_imx6q() || cpu_is_imx6dl())
imx_smp_prepare();
imx_anatop_post_resume();
imx_gpc_post_resume();
imx6q_enable_rbc(false);
imx6_enable_rbc(false);
imx6q_enable_wb(false);
imx6q_set_int_mem_clk_lpm(true);
imx6q_set_lpm(WAIT_CLOCKED);

22
arch/arm/mach-mediatek/Kconfig
View File

@ -1,6 +1,26 @@
config ARCH_MEDIATEK
menuconfig ARCH_MEDIATEK
bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7
select ARM_GIC
select MTK_TIMER
help
Support for Mediatek MT65xx & MT81xx SoCs
if ARCH_MEDIATEK
config MACH_MT6589
bool "MediaTek MT6589 SoCs support"
default ARCH_MEDIATEK
config MACH_MT6592
bool "MediaTek MT6592 SoCs support"
default ARCH_MEDIATEK
config MACH_MT8127
bool "MediaTek MT8127 SoCs support"
default ARCH_MEDIATEK
config MACH_MT8135
bool "MediaTek MT8135 SoCs support"
default ARCH_MEDIATEK
endif

58
arch/arm/mach-mvebu/coherency.c
View File

@ -33,6 +33,7 @@
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#include <asm/dma-mapping.h>
#include "coherency.h"
#include "mvebu-soc-id.h"
@ -76,54 +77,6 @@ int set_cpu_coherent(void)
return ll_enable_coherency();
}
static inline void mvebu_hwcc_sync_io_barrier(void)
{
writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
}
static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size,
enum dma_data_direction dir,
struct dma_attrs *attrs)
{
if (dir != DMA_TO_DEVICE)
mvebu_hwcc_sync_io_barrier();
return pfn_to_dma(dev, page_to_pfn(page)) + offset;
}
static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
size_t size, enum dma_data_direction dir,
struct dma_attrs *attrs)
{
if (dir != DMA_TO_DEVICE)
mvebu_hwcc_sync_io_barrier();
}
static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
size_t size, enum dma_data_direction dir)
{
if (dir != DMA_TO_DEVICE)
mvebu_hwcc_sync_io_barrier();
}
static struct dma_map_ops mvebu_hwcc_dma_ops = {
.alloc = arm_dma_alloc,
.free = arm_dma_free,
.mmap = arm_dma_mmap,
.map_page = mvebu_hwcc_dma_map_page,
.unmap_page = mvebu_hwcc_dma_unmap_page,
.get_sgtable = arm_dma_get_sgtable,
.map_sg = arm_dma_map_sg,
.unmap_sg = arm_dma_unmap_sg,
.sync_single_for_cpu = mvebu_hwcc_dma_sync,
.sync_single_for_device = mvebu_hwcc_dma_sync,
.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
.sync_sg_for_device = arm_dma_sync_sg_for_device,
.set_dma_mask = arm_dma_set_mask,
};
static int mvebu_hwcc_notifier(struct notifier_block *nb,
unsigned long event, void *__dev)
{
@ -131,7 +84,7 @@ static int mvebu_hwcc_notifier(struct notifier_block *nb,
if (event != BUS_NOTIFY_ADD_DEVICE)
return NOTIFY_DONE;
set_dma_ops(dev, &mvebu_hwcc_dma_ops);
set_dma_ops(dev, &arm_coherent_dma_ops);
return NOTIFY_OK;
}
@ -253,14 +206,9 @@ static int coherency_type(void)
return type;
}
/*
* As a precaution, we currently completely disable hardware I/O
* coherency, until enough testing is done with automatic I/O
* synchronization barriers to validate that it is a proper solution.
*/
int coherency_available(void)
{
return false;
return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
}
int __init coherency_init(void)

18
arch/arm/mach-mvebu/mvebu-soc-id.h
View File

@ -20,10 +20,28 @@
#define MV78XX0_A0_REV 0x1
#define MV78XX0_B0_REV 0x2
/* Amada 370 ID */
#define ARMADA_370_DEV_ID 0x6710
/* Amada 370 Revision */
#define ARMADA_370_A1_REV 0x1
/* Armada 375 ID */
#define ARMADA_375_DEV_ID 0x6720
/* Armada 375 */
#define ARMADA_375_Z1_REV 0x0
#define ARMADA_375_A0_REV 0x3
/* Armada 38x ID */
#define ARMADA_380_DEV_ID 0x6810
#define ARMADA_385_DEV_ID 0x6820
#define ARMADA_388_DEV_ID 0x6828
/* Armada 38x Revision */
#define ARMADA_38x_Z1_REV 0x0
#define ARMADA_38x_A0_REV 0x4
#ifdef CONFIG_ARCH_MVEBU
int mvebu_get_soc_id(u32 *dev, u32 *rev);
#else

4
arch/arm/mach-omap2/Makefile
View File

@ -121,6 +121,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
obj-$(CONFIG_SOC_TI81XX) += $(am33xx-43xx-prcm-common)
obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
$(am33xx-43xx-prcm-common)
@ -171,6 +172,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_TI81XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_TI81XX) += clockdomains81xx_data.o
obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
@ -223,6 +226,7 @@ obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o
obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o
obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o

36
arch/arm/mach-omap2/board-generic.c
View File

@ -162,6 +162,42 @@ DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
MACHINE_END
#endif
#ifdef CONFIG_SOC_TI81XX
static const char *const ti814x_boards_compat[] __initconst = {
"ti,dm8148",
"ti,dm814",
NULL,
};
DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = ti81xx_map_io,
.init_early = ti814x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
.init_time = omap3_gptimer_timer_init,
.dt_compat = ti814x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
static const char *const ti816x_boards_compat[] __initconst = {
"ti,dm8168",
"ti,dm816",
NULL,
};
DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = ti81xx_map_io,
.init_early = ti816x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
.init_time = omap3_gptimer_timer_init,
.dt_compat = ti816x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX
static const char *const am33xx_boards_compat[] __initconst = {
"ti,am33xx",

1
arch/arm/mach-omap2/clockdomain.h
View File

@ -216,6 +216,7 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init ti81xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void __init dra7xx_clockdomains_init(void);

194
arch/arm/mach-omap2/clockdomains81xx_data.c Normal file
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@ -0,0 +1,194 @@
/*
* TI81XX Clock Domain data.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "cm81xx.h"
/*
* Note that 814x seems to have HWSUP_SWSUP for many clockdomains
* while 816x does not. According to the TRM, 816x only has HWSUP
* for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
* seems to have the related ifdef the wrong way around claiming
* 816x supports HWSUP while 814x does not. For now, we only set
* HWSUP for ALWON_L3_FAST as that seems to be supported for both
* dm814x and dm816x.
*/
/* Common for 81xx */
static struct clockdomain alwon_l3_slow_81xx_clkdm = {
.name = "alwon_l3s_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain alwon_l3_med_81xx_clkdm = {
.name = "alwon_l3_med_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain alwon_l3_fast_81xx_clkdm = {
.name = "alwon_l3_fast_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain alwon_ethernet_81xx_clkdm = {
.name = "alwon_ethernet_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_ETHERNET_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain mmu_81xx_clkdm = {
.name = "mmu_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_MMU_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain mmu_cfg_81xx_clkdm = {
.name = "mmu_cfg_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_MMUCFG_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
/* 816x only */
static struct clockdomain alwon_mpu_816x_clkdm = {
.name = "alwon_mpu_clkdm",
.pwrdm = { .name = "alwon_pwrdm" },
.cm_inst = TI81XX_CM_ALWON_MOD,
.clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain active_gem_816x_clkdm = {
.name = "active_gem_clkdm",
.pwrdm = { .name = "active_pwrdm" },
.cm_inst = TI816X_CM_ACTIVE_MOD,
.clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain ivahd0_816x_clkdm = {
.name = "ivahd0_clkdm",
.pwrdm = { .name = "ivahd0_pwrdm" },
.cm_inst = TI816X_CM_IVAHD0_MOD,
.clkdm_offs = TI816X_CM_IVAHD0_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain ivahd1_816x_clkdm = {
.name = "ivahd1_clkdm",
.pwrdm = { .name = "ivahd1_pwrdm" },
.cm_inst = TI816X_CM_IVAHD1_MOD,
.clkdm_offs = TI816X_CM_IVAHD1_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain ivahd2_816x_clkdm = {
.name = "ivahd2_clkdm",
.pwrdm = { .name = "ivahd2_pwrdm" },
.cm_inst = TI816X_CM_IVAHD2_MOD,
.clkdm_offs = TI816X_CM_IVAHD2_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain sgx_816x_clkdm = {
.name = "sgx_clkdm",
.pwrdm = { .name = "sgx_pwrdm" },
.cm_inst = TI816X_CM_SGX_MOD,
.clkdm_offs = TI816X_CM_SGX_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain default_l3_med_816x_clkdm = {
.name = "default_l3_med_clkdm",
.pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain default_ducati_816x_clkdm = {
.name = "default_ducati_clkdm",
.pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain default_pci_816x_clkdm = {
.name = "default_pci_clkdm",
.pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain default_l3_slow_816x_clkdm = {
.name = "default_l3_slow_clkdm",
.pwrdm = { .name = "default_pwrdm" },
.cm_inst = TI816X_CM_DEFAULT_MOD,
.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain *clockdomains_ti81xx[] __initdata = {
&alwon_mpu_816x_clkdm,
&alwon_l3_slow_81xx_clkdm,
&alwon_l3_med_81xx_clkdm,
&alwon_l3_fast_81xx_clkdm,
&alwon_ethernet_81xx_clkdm,
&mmu_81xx_clkdm,
&mmu_cfg_81xx_clkdm,
&active_gem_816x_clkdm,
&ivahd0_816x_clkdm,
&ivahd1_816x_clkdm,
&ivahd2_816x_clkdm,
&sgx_816x_clkdm,
&default_l3_med_816x_clkdm,
&default_ducati_816x_clkdm,
&default_pci_816x_clkdm,
&default_l3_slow_816x_clkdm,
NULL,
};
void __init ti81xx_clockdomains_init(void)
{
clkdm_register_platform_funcs(&am33xx_clkdm_operations);
clkdm_register_clkdms(clockdomains_ti81xx);
clkdm_complete_init();
}
#endif

61
arch/arm/mach-omap2/cm81xx.h Normal file
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@ -0,0 +1,61 @@
/*
* Clock domain register offsets for TI81XX.
*
* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
/* TI81XX common CM module offsets */
#define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
/* TI816X CM module offsets */
#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */
#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */
#define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
#define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
#define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
#define TI816X_CM_SGX_MOD 0x0900 /* 256B */
/* ALWON */
#define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
#define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
#define TI81XX_CM_ETHERNET_CLKDM 0x0004
#define TI81XX_CM_MMU_CLKDM 0x000C
#define TI81XX_CM_MMUCFG_CLKDM 0x0010
#define TI81XX_CM_ALWON_MPU_CLKDM 0x001C
#define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030
/* ACTIVE */
#define TI816X_CM_ACTIVE_GEM_CLKDM 0x0000
/* IVAHD0 */
#define TI816X_CM_IVAHD0_CLKDM 0x0000
/* IVAHD1 */
#define TI816X_CM_IVAHD1_CLKDM 0x0000
/* IVAHD2 */
#define TI816X_CM_IVAHD2_CLKDM 0x0000
/* SGX */
#define TI816X_CM_SGX_CLKDM 0x0000
/* DEFAULT */
#define TI816X_CM_DEFAULT_L3_MED_CLKDM 0x0004
#define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010
#define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
#define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018
#endif

82
arch/arm/mach-omap2/io.c
View File

@ -492,44 +492,6 @@ void __init am35xx_init_early(void)
omap_clk_soc_init = am35xx_dt_clk_init;
}
void __init ti814x_init_early(void)
{
omap2_set_globals_tap(TI814X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
ti81xx_check_features();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
}
void __init ti816x_init_early(void)
{
omap2_set_globals_tap(TI816X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
ti81xx_check_features();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
}
void __init omap3_init_late(void)
{
omap_common_late_init();
@ -572,6 +534,50 @@ void __init ti81xx_init_late(void)
}
#endif
#ifdef CONFIG_SOC_TI81XX
void __init ti814x_init_early(void)
{
omap2_set_globals_tap(TI814X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
ti81xx_check_features();
am33xx_prm_init();
am33xx_cm_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti81xx_clockdomains_init();
ti81xx_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
}
void __init ti816x_init_early(void)
{
omap2_set_globals_tap(TI816X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
ti81xx_check_features();
am33xx_prm_init();
am33xx_cm_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti81xx_clockdomains_init();
ti81xx_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
}
#endif
#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{

2
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -3916,7 +3916,7 @@ void __init omap_hwmod_init(void)
soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
soc_ops.init_clkdm = _init_clkdm;
} else if (soc_is_am33xx()) {
} else if (cpu_is_ti816x() || soc_is_am33xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;

1
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -748,6 +748,7 @@ extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int ti81xx_hwmod_init(void);
extern int dra7xx_hwmod_init(void);
int am43xx_hwmod_init(void);

1136
arch/arm/mach-omap2/omap_hwmod_81xx_data.c Normal file
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File diff suppressed because it is too large Load Diff

22
arch/arm/mach-prima2/Kconfig
View File

@ -11,7 +11,7 @@ menuconfig ARCH_SIRF
if ARCH_SIRF
comment "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
config ARCH_ATLAS6
bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
@ -20,6 +20,17 @@ config ARCH_ATLAS6
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config ARCH_ATLAS7
bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
default y
select ARM_GIC
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select SMP_ON_UP if SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform
config ARCH_PRIMA2
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
default y
@ -28,15 +39,6 @@ config ARCH_PRIMA2
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config ARCH_MARCO
bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
default y
select ARM_GIC
select HAVE_ARM_SCU if SMP
select SMP_ON_UP if SMP
help
Support for CSR SiRFSoC ARM Cortex A9 Platform
config SIRF_IRQ
bool

1
arch/arm/mach-prima2/Makefile
View File

@ -1,7 +1,6 @@
obj-y += rstc.o
obj-y += common.o
obj-y += rtciobrg.o
obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

22
arch/arm/mach-prima2/common.c
View File

@ -20,12 +20,6 @@ static void __init sirfsoc_init_late(void)
sirfsoc_pm_init();
}
static __init void sirfsoc_map_io(void)
{
sirfsoc_map_lluart();
sirfsoc_map_scu();
}
#ifdef CONFIG_ARCH_ATLAS6
static const char *atlas6_dt_match[] __initconst = {
"sirf,atlas6",
@ -36,7 +30,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.map_io = sirfsoc_map_io,
.init_late = sirfsoc_init_late,
.dt_compat = atlas6_dt_match,
MACHINE_END
@ -52,26 +45,21 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.map_io = sirfsoc_map_io,
.dma_zone_size = SZ_256M,
.init_late = sirfsoc_init_late,
.dt_compat = prima2_dt_match,
MACHINE_END
#endif
#ifdef CONFIG_ARCH_MARCO
static const char *marco_dt_match[] __initconst = {
"sirf,marco",
#ifdef CONFIG_ARCH_ATLAS7
static const char *atlas7_dt_match[] __initdata = {
"sirf,atlas7",
NULL
};
DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
.smp = smp_ops(sirfsoc_smp_ops),
.map_io = sirfsoc_map_io,
.init_late = sirfsoc_init_late,
.dt_compat = marco_dt_match,
.dt_compat = atlas7_dt_match,
MACHINE_END
#endif

35
arch/arm/mach-prima2/lluart.c
View File

@ -1,35 +0,0 @@
/*
* Static memory mapping for DEBUG_LL
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <linux/kernel.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include "common.h"
#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
#define SIRFSOC_UART1_PA_BASE 0xb0060000
#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
#define SIRFSOC_UART1_PA_BASE 0xcc060000
#else
#define SIRFSOC_UART1_PA_BASE 0
#endif
#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
#define SIRFSOC_UART1_SIZE SZ_4K
void __init sirfsoc_map_lluart(void)
{
struct map_desc sirfsoc_lluart_map = {
.virtual = SIRFSOC_UART1_VA_BASE,
.pfn = __phys_to_pfn(SIRFSOC_UART1_PA_BASE),
.length = SIRFSOC_UART1_SIZE,
.type = MT_DEVICE,
};
iotable_init(&sirfsoc_lluart_map, 1);
}

52
arch/arm/mach-prima2/platsmp.c
View File

@ -20,30 +20,10 @@
#include "common.h"
static void __iomem *scu_base;
static void __iomem *rsc_base;
static void __iomem *clk_base;
static DEFINE_SPINLOCK(boot_lock);
static struct map_desc scu_io_desc __initdata = {
.length = SZ_4K,
.type = MT_DEVICE,
};
void __init sirfsoc_map_scu(void)
{
unsigned long base;
/* Get SCU base */
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
scu_io_desc.virtual = SIRFSOC_VA(base);
scu_io_desc.pfn = __phys_to_pfn(base);
iotable_init(&scu_io_desc, 1);
scu_base = (void __iomem *)SIRFSOC_VA(base);
}
static void sirfsoc_secondary_init(unsigned int cpu)
{
/*
@ -60,8 +40,8 @@ static void sirfsoc_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static struct of_device_id rsc_ids[] = {
{ .compatible = "sirf,marco-rsc" },
static struct of_device_id clk_ids[] = {
{ .compatible = "sirf,atlas7-clkc" },
{},
};
@ -70,27 +50,27 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
unsigned long timeout;
struct device_node *np;
np = of_find_matching_node(NULL, rsc_ids);
np = of_find_matching_node(NULL, clk_ids);
if (!np)
return -ENODEV;
rsc_base = of_iomap(np, 0);
if (!rsc_base)
clk_base = of_iomap(np, 0);
if (!clk_base)
return -ENOMEM;
/*
* write the address of secondary startup into the sram register
* at offset 0x2C, then write the magic number 0x3CAF5D62 to the
* RSC register at offset 0x28, which is what boot rom code is
* write the address of secondary startup into the clkc register
* at offset 0x2bC, then write the magic number 0x3CAF5D62 to the
* clkc register at offset 0x2b8, which is what boot rom code is
* waiting for. This would wake up the secondary core from WFE
*/
#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
__raw_writel(virt_to_phys(sirfsoc_secondary_startup),
rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
__raw_writel(0x3CAF5D62,
rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
/* make sure write buffer is drained */
mb();
@ -132,13 +112,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
return pen_release != -1 ? -ENOSYS : 0;
}
static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
{
scu_enable(scu_base);
}
struct smp_operations sirfsoc_smp_ops __initdata = {
.smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
.smp_secondary_init = sirfsoc_secondary_init,
.smp_boot_secondary = sirfsoc_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU

17
arch/arm/mach-prima2/rstc.c
View File

@ -34,7 +34,6 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
mutex_lock(&rstc_lock);
if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
/*
* Writing 1 to this bit resets corresponding block.
* Writing 0 to this bit de-asserts reset signal of the
@ -49,21 +48,6 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
writel(readl(sirfsoc_rstc_base +
(reset_bit / 32) * 4) & ~(1 << reset_bit),
sirfsoc_rstc_base + (reset_bit / 32) * 4);
} else {
/*
* For MARCO and POLO
* Writing 1 to SET register resets corresponding block.
* Writing 1 to CLEAR register de-asserts reset signal of the
* corresponding block.
* datasheet doesn't require explicit delay between the set and
* clear of reset bit. it could be shorter if tests pass.
*/
writel(1 << reset_bit,
sirfsoc_rstc_base + (reset_bit / 32) * 8);
msleep(20);
writel(1 << reset_bit,
sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
}
mutex_unlock(&rstc_lock);
@ -106,7 +90,6 @@ static int sirfsoc_rstc_probe(struct platform_device *pdev)
static const struct of_device_id rstc_ids[] = {
{ .compatible = "sirf,prima2-rstc" },
{ .compatible = "sirf,marco-rstc" },
{},
};

1
arch/arm/mach-prima2/rtciobrg.c
View File

@ -104,7 +104,6 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
static const struct of_device_id rtciobrg_ids[] = {
{ .compatible = "sirf,prima2-rtciobg" },
{ .compatible = "sirf,marco-rtciobg" },
{}
};

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