diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
index 5f2f82ed9598..c6c69d0a8d01 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
@@ -1,7 +1,6 @@
-#ifndef __NOUVEAU_MSPPP_H__
-#define __NOUVEAU_MSPPP_H__
-
-extern struct nouveau_oclass nv98_msppp_oclass;
-extern struct nouveau_oclass nvc0_msppp_oclass;
-
+#ifndef __NVKM_MSPPP_H__
+#define __NVKM_MSPPP_H__
+#include <core/engine.h>
+extern struct nvkm_oclass g98_msppp_oclass;
+extern struct nvkm_oclass gf100_msppp_oclass;
 #endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 67db4e6ca489..a5a9c8bf8f0d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device)
 #if 0
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 #endif
 		break;
 	case 0x124:
@@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 #endif
 		break;
 	default:
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 9ea3a60ab417..a7838a7c1901 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -257,7 +257,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
@@ -315,7 +315,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
@@ -344,7 +344,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
@@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
@@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
@@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
@@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index ff39357a2bf2..83dd982b1c4c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
@@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
@@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 56c3e67b8962..5676a0251c79 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nve0_pm_oclass;
 		break;
 	case 0xe7:
@@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nve0_pm_oclass;
 		break;
 	case 0xe6:
@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nve0_pm_oclass;
 		break;
 	case 0xea:
@@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvf0_pm_oclass;
 		break;
 	case 0xf1:
@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvf0_pm_oclass;
 		break;
 	case 0x106:
@@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		break;
 	case 0x108:
 		device->cname = "GK208";
@@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
-		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
+		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		break;
 	default:
 		nv_fatal(device, "unknown Kepler chipset\n");
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
index 9b90ce948425..4576a9eee39d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
@@ -1,2 +1,2 @@
-nvkm-y += nvkm/engine/msppp/nv98.o
-nvkm-y += nvkm/engine/msppp/nvc0.o
+nvkm-y += nvkm/engine/msppp/g98.o
+nvkm-y += nvkm/engine/msppp/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
similarity index 62%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
index c044943c3fc7..7a602a2dec94 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
@@ -21,22 +21,21 @@
  *
  * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
  */
-
-#include <engine/falcon.h>
 #include <engine/msppp.h>
+#include <engine/falcon.h>
 
-struct nv98_msppp_priv {
-	struct nouveau_falcon base;
+struct g98_msppp_priv {
+	struct nvkm_falcon base;
 };
 
 /*******************************************************************************
  * MSPPP object classes
  ******************************************************************************/
 
-static struct nouveau_oclass
-nv98_msppp_sclass[] = {
-	{ 0x88b3, &nouveau_object_ofuncs },
-	{ 0x85b3, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+g98_msppp_sclass[] = {
+	{ 0x88b3, &nvkm_object_ofuncs },
+	{ 0x85b3, &nvkm_object_ofuncs },
 	{},
 };
 
@@ -44,16 +43,16 @@ nv98_msppp_sclass[] = {
  * PMSPPP context
  ******************************************************************************/
 
-static struct nouveau_oclass
-nv98_msppp_cclass = {
+static struct nvkm_oclass
+g98_msppp_cclass = {
 	.handle = NV_ENGCTX(MSPPP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
+	.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = _nvkm_falcon_context_ctor,
+		.dtor = _nvkm_falcon_context_dtor,
+		.init = _nvkm_falcon_context_init,
+		.fini = _nvkm_falcon_context_fini,
+		.rd32 = _nvkm_falcon_context_rd32,
+		.wr32 = _nvkm_falcon_context_wr32,
 	},
 };
 
@@ -62,12 +61,12 @@ nv98_msppp_cclass = {
  ******************************************************************************/
 
 static int
-nv98_msppp_init(struct nouveau_object *object)
+g98_msppp_init(struct nvkm_object *object)
 {
-	struct nv98_msppp_priv *priv = (void *)object;
+	struct g98_msppp_priv *priv = (void *)object;
 	int ret;
 
-	ret = nouveau_falcon_init(&priv->base);
+	ret = nvkm_falcon_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -77,34 +76,34 @@ nv98_msppp_init(struct nouveau_object *object)
 }
 
 static int
-nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
+g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	       struct nvkm_oclass *oclass, void *data, u32 size,
+	       struct nvkm_object **pobject)
 {
-	struct nv98_msppp_priv *priv;
+	struct g98_msppp_priv *priv;
 	int ret;
 
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
-				    "PMSPPP", "msppp", &priv);
+	ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true,
+				 "PMSPPP", "msppp", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00400002;
-	nv_engine(priv)->cclass = &nv98_msppp_cclass;
-	nv_engine(priv)->sclass = nv98_msppp_sclass;
+	nv_engine(priv)->cclass = &g98_msppp_cclass;
+	nv_engine(priv)->sclass = g98_msppp_sclass;
 	return 0;
 }
 
-struct nouveau_oclass
-nv98_msppp_oclass = {
+struct nvkm_oclass
+g98_msppp_oclass = {
 	.handle = NV_ENGINE(MSPPP, 0x98),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv98_msppp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nv98_msppp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
+	.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = g98_msppp_ctor,
+		.dtor = _nvkm_falcon_dtor,
+		.init = g98_msppp_init,
+		.fini = _nvkm_falcon_fini,
+		.rd32 = _nvkm_falcon_rd32,
+		.wr32 = _nvkm_falcon_wr32,
 	},
 };
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
similarity index 61%
rename from drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
index 91398e639395..6047baee1f75 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
@@ -21,21 +21,20 @@
  *
  * Authors: Maarten Lankhorst
  */
-
-#include <engine/falcon.h>
 #include <engine/msppp.h>
+#include <engine/falcon.h>
 
-struct nvc0_msppp_priv {
-	struct nouveau_falcon base;
+struct gf100_msppp_priv {
+	struct nvkm_falcon base;
 };
 
 /*******************************************************************************
  * MSPPP object classes
  ******************************************************************************/
 
-static struct nouveau_oclass
-nvc0_msppp_sclass[] = {
-	{ 0x90b3, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gf100_msppp_sclass[] = {
+	{ 0x90b3, &nvkm_object_ofuncs },
 	{},
 };
 
@@ -43,16 +42,16 @@ nvc0_msppp_sclass[] = {
  * PMSPPP context
  ******************************************************************************/
 
-static struct nouveau_oclass
-nvc0_msppp_cclass = {
+static struct nvkm_oclass
+gf100_msppp_cclass = {
 	.handle = NV_ENGCTX(MSPPP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = _nouveau_falcon_context_ctor,
-		.dtor = _nouveau_falcon_context_dtor,
-		.init = _nouveau_falcon_context_init,
-		.fini = _nouveau_falcon_context_fini,
-		.rd32 = _nouveau_falcon_context_rd32,
-		.wr32 = _nouveau_falcon_context_wr32,
+	.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = _nvkm_falcon_context_ctor,
+		.dtor = _nvkm_falcon_context_dtor,
+		.init = _nvkm_falcon_context_init,
+		.fini = _nvkm_falcon_context_fini,
+		.rd32 = _nvkm_falcon_context_rd32,
+		.wr32 = _nvkm_falcon_context_wr32,
 	},
 };
 
@@ -61,12 +60,12 @@ nvc0_msppp_cclass = {
  ******************************************************************************/
 
 static int
-nvc0_msppp_init(struct nouveau_object *object)
+gf100_msppp_init(struct nvkm_object *object)
 {
-	struct nvc0_msppp_priv *priv = (void *)object;
+	struct gf100_msppp_priv *priv = (void *)object;
 	int ret;
 
-	ret = nouveau_falcon_init(&priv->base);
+	ret = nvkm_falcon_init(&priv->base);
 	if (ret)
 		return ret;
 
@@ -76,35 +75,35 @@ nvc0_msppp_init(struct nouveau_object *object)
 }
 
 static int
-nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	      struct nouveau_oclass *oclass, void *data, u32 size,
-	      struct nouveau_object **pobject)
+gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		 struct nvkm_oclass *oclass, void *data, u32 size,
+		 struct nvkm_object **pobject)
 {
-	struct nvc0_msppp_priv *priv;
+	struct gf100_msppp_priv *priv;
 	int ret;
 
-	ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
-				    "PMSPPP", "msppp", &priv);
+	ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true,
+				 "PMSPPP", "msppp", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
 	nv_subdev(priv)->unit = 0x00000002;
-	nv_subdev(priv)->intr = nouveau_falcon_intr;
-	nv_engine(priv)->cclass = &nvc0_msppp_cclass;
-	nv_engine(priv)->sclass = nvc0_msppp_sclass;
+	nv_subdev(priv)->intr = nvkm_falcon_intr;
+	nv_engine(priv)->cclass = &gf100_msppp_cclass;
+	nv_engine(priv)->sclass = gf100_msppp_sclass;
 	return 0;
 }
 
-struct nouveau_oclass
-nvc0_msppp_oclass = {
+struct nvkm_oclass
+gf100_msppp_oclass = {
 	.handle = NV_ENGINE(MSPPP, 0xc0),
-	.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvc0_msppp_ctor,
-		.dtor = _nouveau_falcon_dtor,
-		.init = nvc0_msppp_init,
-		.fini = _nouveau_falcon_fini,
-		.rd32 = _nouveau_falcon_rd32,
-		.wr32 = _nouveau_falcon_wr32,
+	.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = gf100_msppp_ctor,
+		.dtor = _nvkm_falcon_dtor,
+		.init = gf100_msppp_init,
+		.fini = _nvkm_falcon_fini,
+		.rd32 = _nvkm_falcon_rd32,
+		.wr32 = _nvkm_falcon_wr32,
 	},
 };