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drm/nouveau/msvld: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-01-14 15:30:40 +10:00
parent 87a876579a
commit 87c33f4e9f
9 changed files with 141 additions and 143 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
View File

@ -1,6 +1,7 @@
#ifndef __NVKM_MSVLD_H__
#define __NVKM_MSVLD_H__
extern struct nouveau_oclass nv98_msvld_oclass;
extern struct nouveau_oclass nvc0_msvld_oclass;
extern struct nouveau_oclass nve0_msvld_oclass;
#include <core/engine.h>
extern struct nvkm_oclass g98_msvld_oclass;
extern struct nvkm_oclass gf100_msvld_oclass;
extern struct nvkm_oclass gk104_msvld_oclass;
#endif

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -94,7 +94,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif
@ -137,7 +137,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
#endif

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -256,7 +256,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@ -343,7 +343,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass;
@ -373,7 +373,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@ -403,7 +403,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@ -433,7 +433,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@ -463,7 +463,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gt215_ce_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;

18
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View File

@ -85,7 +85,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@ -118,7 +118,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@ -151,7 +151,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@ -183,7 +183,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@ -216,7 +216,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@ -248,7 +248,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
@ -280,7 +280,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
@ -313,7 +313,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
@ -343,7 +343,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View File

@ -88,7 +88,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@ -122,7 +122,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@ -156,7 +156,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass;
@ -212,7 +212,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
@ -246,7 +246,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass;
@ -280,7 +280,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
@ -313,7 +313,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;

6
drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
View File

@ -1,3 +1,3 @@
nvkm-y += nvkm/engine/msvld/nv98.o
nvkm-y += nvkm/engine/msvld/nvc0.o
nvkm-y += nvkm/engine/msvld/nve0.o
nvkm-y += nvkm/engine/msvld/g98.o
nvkm-y += nvkm/engine/msvld/gf100.o
nvkm-y += nvkm/engine/msvld/gk104.o

75
drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c → drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c
View File

@ -21,23 +21,22 @@
*
* Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
*/
#include <engine/falcon.h>
#include <engine/msvld.h>
#include <engine/falcon.h>
struct nv98_msvld_priv {
struct nouveau_falcon base;
struct g98_msvld_priv {
struct nvkm_falcon base;
};
/*******************************************************************************
* MSVLD object classes
******************************************************************************/
static struct nouveau_oclass
nv98_msvld_sclass[] = {
{ 0x88b1, &nouveau_object_ofuncs },
{ 0x85b1, &nouveau_object_ofuncs },
{ 0x86b1, &nouveau_object_ofuncs },
static struct nvkm_oclass
g98_msvld_sclass[] = {
{ 0x88b1, &nvkm_object_ofuncs },
{ 0x85b1, &nvkm_object_ofuncs },
{ 0x86b1, &nvkm_object_ofuncs },
{},
};
@ -45,16 +44,16 @@ nv98_msvld_sclass[] = {
* PMSVLD context
******************************************************************************/
static struct nouveau_oclass
nv98_msvld_cclass = {
static struct nvkm_oclass
g98_msvld_cclass = {
.handle = NV_ENGCTX(MSVLD, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
.init = _nouveau_falcon_context_init,
.fini = _nouveau_falcon_context_fini,
.rd32 = _nouveau_falcon_context_rd32,
.wr32 = _nouveau_falcon_context_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_falcon_context_ctor,
.dtor = _nvkm_falcon_context_dtor,
.init = _nvkm_falcon_context_init,
.fini = _nvkm_falcon_context_fini,
.rd32 = _nvkm_falcon_context_rd32,
.wr32 = _nvkm_falcon_context_wr32,
},
};
@ -63,12 +62,12 @@ nv98_msvld_cclass = {
******************************************************************************/
static int
nv98_msvld_init(struct nouveau_object *object)
g98_msvld_init(struct nvkm_object *object)
{
struct nv98_msvld_priv *priv = (void *)object;
struct g98_msvld_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@ -78,34 +77,34 @@ nv98_msvld_init(struct nouveau_object *object)
}
static int
nv98_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv98_msvld_priv *priv;
struct g98_msvld_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
"PMSVLD", "msvld", &priv);
ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true,
"PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x04008000;
nv_engine(priv)->cclass = &nv98_msvld_cclass;
nv_engine(priv)->sclass = nv98_msvld_sclass;
nv_engine(priv)->cclass = &g98_msvld_cclass;
nv_engine(priv)->sclass = g98_msvld_sclass;
return 0;
}
struct nouveau_oclass
nv98_msvld_oclass = {
struct nvkm_oclass
g98_msvld_oclass = {
.handle = NV_ENGINE(MSVLD, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv98_msvld_ctor,
.dtor = _nouveau_falcon_dtor,
.init = nv98_msvld_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g98_msvld_ctor,
.dtor = _nvkm_falcon_dtor,
.init = g98_msvld_init,
.fini = _nvkm_falcon_fini,
.rd32 = _nvkm_falcon_rd32,
.wr32 = _nvkm_falcon_wr32,
},
};

73
drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c → drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c
View File

@ -21,21 +21,20 @@
*
* Authors: Maarten Lankhorst
*/
#include <engine/falcon.h>
#include <engine/msvld.h>
#include <engine/falcon.h>
struct nvc0_msvld_priv {
struct nouveau_falcon base;
struct gf100_msvld_priv {
struct nvkm_falcon base;
};
/*******************************************************************************
* MSVLD object classes
******************************************************************************/
static struct nouveau_oclass
nvc0_msvld_sclass[] = {
{ 0x90b1, &nouveau_object_ofuncs },
static struct nvkm_oclass
gf100_msvld_sclass[] = {
{ 0x90b1, &nvkm_object_ofuncs },
{},
};
@ -43,16 +42,16 @@ nvc0_msvld_sclass[] = {
* PMSVLD context
******************************************************************************/
static struct nouveau_oclass
nvc0_msvld_cclass = {
static struct nvkm_oclass
gf100_msvld_cclass = {
.handle = NV_ENGCTX(MSVLD, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
.init = _nouveau_falcon_context_init,
.fini = _nouveau_falcon_context_fini,
.rd32 = _nouveau_falcon_context_rd32,
.wr32 = _nouveau_falcon_context_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_falcon_context_ctor,
.dtor = _nvkm_falcon_context_dtor,
.init = _nvkm_falcon_context_init,
.fini = _nvkm_falcon_context_fini,
.rd32 = _nvkm_falcon_context_rd32,
.wr32 = _nvkm_falcon_context_wr32,
},
};
@ -61,12 +60,12 @@ nvc0_msvld_cclass = {
******************************************************************************/
static int
nvc0_msvld_init(struct nouveau_object *object)
gf100_msvld_init(struct nvkm_object *object)
{
struct nvc0_msvld_priv *priv = (void *)object;
struct gf100_msvld_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@ -76,35 +75,35 @@ nvc0_msvld_init(struct nouveau_object *object)
}
static int
nvc0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvc0_msvld_priv *priv;
struct gf100_msvld_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
"PMSVLD", "msvld", &priv);
ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true,
"PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00008000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
nv_engine(priv)->cclass = &nvc0_msvld_cclass;
nv_engine(priv)->sclass = nvc0_msvld_sclass;
nv_subdev(priv)->intr = nvkm_falcon_intr;
nv_engine(priv)->cclass = &gf100_msvld_cclass;
nv_engine(priv)->sclass = gf100_msvld_sclass;
return 0;
}
struct nouveau_oclass
nvc0_msvld_oclass = {
struct nvkm_oclass
gf100_msvld_oclass = {
.handle = NV_ENGINE(MSVLD, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_msvld_ctor,
.dtor = _nouveau_falcon_dtor,
.init = nvc0_msvld_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_msvld_ctor,
.dtor = _nvkm_falcon_dtor,
.init = gf100_msvld_init,
.fini = _nvkm_falcon_fini,
.rd32 = _nvkm_falcon_rd32,
.wr32 = _nvkm_falcon_wr32,
},
};

73
drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c → drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c
View File

@ -21,21 +21,20 @@
*
* Authors: Ben Skeggs
*/
#include <engine/falcon.h>
#include <engine/msvld.h>
#include <engine/falcon.h>
struct nve0_msvld_priv {
struct nouveau_falcon base;
struct gk104_msvld_priv {
struct nvkm_falcon base;
};
/*******************************************************************************
* MSVLD object classes
******************************************************************************/
static struct nouveau_oclass
nve0_msvld_sclass[] = {
{ 0x95b1, &nouveau_object_ofuncs },
static struct nvkm_oclass
gk104_msvld_sclass[] = {
{ 0x95b1, &nvkm_object_ofuncs },
{},
};
@ -43,16 +42,16 @@ nve0_msvld_sclass[] = {
* PMSVLD context
******************************************************************************/
static struct nouveau_oclass
nve0_msvld_cclass = {
static struct nvkm_oclass
gk104_msvld_cclass = {
.handle = NV_ENGCTX(MSVLD, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
.init = _nouveau_falcon_context_init,
.fini = _nouveau_falcon_context_fini,
.rd32 = _nouveau_falcon_context_rd32,
.wr32 = _nouveau_falcon_context_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_falcon_context_ctor,
.dtor = _nvkm_falcon_context_dtor,
.init = _nvkm_falcon_context_init,
.fini = _nvkm_falcon_context_fini,
.rd32 = _nvkm_falcon_context_rd32,
.wr32 = _nvkm_falcon_context_wr32,
},
};
@ -61,12 +60,12 @@ nve0_msvld_cclass = {
******************************************************************************/
static int
nve0_msvld_init(struct nouveau_object *object)
gk104_msvld_init(struct nvkm_object *object)
{
struct nve0_msvld_priv *priv = (void *)object;
struct gk104_msvld_priv *priv = (void *)object;
int ret;
ret = nouveau_falcon_init(&priv->base);
ret = nvkm_falcon_init(&priv->base);
if (ret)
return ret;
@ -76,35 +75,35 @@ nve0_msvld_init(struct nouveau_object *object)
}
static int
nve0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nve0_msvld_priv *priv;
struct gk104_msvld_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
"PMSVLD", "msvld", &priv);
ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true,
"PMSVLD", "msvld", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00008000;
nv_subdev(priv)->intr = nouveau_falcon_intr;
nv_engine(priv)->cclass = &nve0_msvld_cclass;
nv_engine(priv)->sclass = nve0_msvld_sclass;
nv_subdev(priv)->intr = nvkm_falcon_intr;
nv_engine(priv)->cclass = &gk104_msvld_cclass;
nv_engine(priv)->sclass = gk104_msvld_sclass;
return 0;
}
struct nouveau_oclass
nve0_msvld_oclass = {
struct nvkm_oclass
gk104_msvld_oclass = {
.handle = NV_ENGINE(MSVLD, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_msvld_ctor,
.dtor = _nouveau_falcon_dtor,
.init = nve0_msvld_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk104_msvld_ctor,
.dtor = _nvkm_falcon_dtor,
.init = gk104_msvld_init,
.fini = _nvkm_falcon_fini,
.rd32 = _nvkm_falcon_rd32,
.wr32 = _nvkm_falcon_wr32,
},
};