mirror of https://gitee.com/openkylin/linux.git
[ARM] pxa: simplify DMA register definitions
1. DRCMRxx is no longer recommended, use DRCMR(xx) instead, and pass DRCMR index by "struct resource" if possible 2. DCSRxx, DDADRxx, DSADRxx, DTADRxx, DCMDxx is never used, use DCSR(), DDADR(), DSADR(), DTADR(), DCMD() instead Signed-off-by: Eric Miao <eric.miao@marvell.com> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Eric Miao
Russell King
parent
cbd18f8e3d
commit
87f3dd7797
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@ -69,24 +69,6 @@
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/*
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* DMA Controller
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*/
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#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
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#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
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#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
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#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
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#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
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#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
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#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
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#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
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#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
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#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
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#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
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#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
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#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
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#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
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#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
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#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
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#define DCSR(x) __REG2(0x40000000, (x) << 2)
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#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
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@ -115,145 +97,9 @@
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&__REG2(0x40000100, ((n) & 0x3f) << 2) : \
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&__REG2(0x40001100, ((n) & 0x3f) << 2)))
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#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
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#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
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#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
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#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
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#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
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#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
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#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
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#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
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#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
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#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
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#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
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#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
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#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
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#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
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#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
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#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
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#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
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#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
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#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
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#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
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#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
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#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
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#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
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#define DRCMR23 __REG(0x4000015c) /* Reserved */
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#define DRCMR24 __REG(0x40000160) /* Reserved */
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#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
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#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
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#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
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#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
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#define DRCMR29 __REG(0x40000174) /* Reserved */
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#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
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#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
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#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
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#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
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#define DRCMR34 __REG(0x40000188) /* Reserved */
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#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
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#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
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#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
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#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
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#define DRCMR39 __REG(0x4000019C) /* Reserved */
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#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
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#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
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#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
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#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
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#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
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#define DRCMRRXSADR DRCMR2
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#define DRCMRTXSADR DRCMR3
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#define DRCMRRXBTRBR DRCMR4
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#define DRCMRTXBTTHR DRCMR5
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#define DRCMRRXFFRBR DRCMR6
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#define DRCMRTXFFTHR DRCMR7
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#define DRCMRRXMCDR DRCMR8
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#define DRCMRRXMODR DRCMR9
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#define DRCMRTXMODR DRCMR10
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#define DRCMRRXPCDR DRCMR11
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#define DRCMRTXPCDR DRCMR12
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#define DRCMRRXSSDR DRCMR13
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#define DRCMRTXSSDR DRCMR14
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#define DRCMRRXSS2DR DRCMR15
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#define DRCMRTXSS2DR DRCMR16
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#define DRCMRRXICDR DRCMR17
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#define DRCMRTXICDR DRCMR18
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#define DRCMRRXSTRBR DRCMR19
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#define DRCMRTXSTTHR DRCMR20
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#define DRCMRRXMMC DRCMR21
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#define DRCMRTXMMC DRCMR22
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#define DRCMRRXSS3DR DRCMR66
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#define DRCMRTXSS3DR DRCMR67
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#define DRCMRUDC(x) DRCMR((x) + 24)
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#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
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#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
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#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
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#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
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#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
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#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
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#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
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#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
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#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
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#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
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#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
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#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
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#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
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#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
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#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
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#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
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#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
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#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
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#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
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#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
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#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
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#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
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#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
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#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
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#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
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#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
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#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
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#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
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#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
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#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
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#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
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#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
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#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
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#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
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#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
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#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
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#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
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#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
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#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
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#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
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#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
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#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
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#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
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#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
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#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
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#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
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#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
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#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
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#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
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#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
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#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
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#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
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#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
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#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
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#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
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#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
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#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
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#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
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#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
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#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
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#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
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#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
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#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
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#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
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#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
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#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
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#define DDADR(x) __REG2(0x40000200, (x) << 4)
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#define DSADR(x) __REG2(0x40000204, (x) << 4)
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#define DTADR(x) __REG2(0x40000208, (x) << 4)
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@ -1025,9 +1025,9 @@ static int pxa_camera_resume(struct soc_camera_device *icd)
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struct pxa_camera_dev *pcdev = ici->priv;
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int i = 0, ret = 0;
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DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
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DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
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DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
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DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
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DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
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DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
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CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB;
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CICR1 = pcdev->save_cicr[i++];
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@ -1171,9 +1171,9 @@ static int pxa_camera_probe(struct platform_device *pdev)
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}
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dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
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DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
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DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
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DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
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DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
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DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
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DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
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/* request irq */
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err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
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@ -572,8 +572,8 @@ static void pxa_irda_startup(struct pxa_irda *si)
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ICCR2 = ICCR2_TXP | ICCR2_TRIG_32;
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/* configure DMAC */
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DRCMR17 = si->rxdma | DRCMR_MAPVLD;
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DRCMR18 = si->txdma | DRCMR_MAPVLD;
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DRCMR(17) = si->rxdma | DRCMR_MAPVLD;
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DRCMR(18) = si->txdma | DRCMR_MAPVLD;
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/* force SIR reinitialization */
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si->speed = 4000000;
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@ -602,8 +602,8 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
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/* disable the STUART or FICP clocks */
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pxa_irda_disable_clk(si);
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DRCMR17 = 0;
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DRCMR18 = 0;
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DRCMR(17) = 0;
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DRCMR(18) = 0;
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local_irq_restore(flags);
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@ -215,7 +215,7 @@ static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
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.name = "AC97 PCM out",
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.dev_addr = __PREG(PCDR),
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.drcmr = &DRCMRTXPCDR,
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.drcmr = &DRCMR(12),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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@ -223,7 +223,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
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.name = "AC97 PCM in",
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.dev_addr = __PREG(PCDR),
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.drcmr = &DRCMRRXPCDR,
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.drcmr = &DRCMR(11),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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@ -244,7 +244,7 @@ struct snd_ac97_bus_ops soc_ac97_ops = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
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.name = "AC97 PCM Stereo out",
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.dev_addr = __PREG(PCDR),
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.drcmr = &DRCMRTXPCDR,
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.drcmr = &DRCMR(12),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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@ -252,7 +252,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
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.name = "AC97 PCM Stereo in",
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.dev_addr = __PREG(PCDR),
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.drcmr = &DRCMRRXPCDR,
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.drcmr = &DRCMR(11),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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@ -260,7 +260,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
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.name = "AC97 Aux PCM (Slot 5) Mono out",
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.dev_addr = __PREG(MODR),
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.drcmr = &DRCMRTXMODR,
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.drcmr = &DRCMR(10),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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@ -268,7 +268,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
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.name = "AC97 Aux PCM (Slot 5) Mono in",
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.dev_addr = __PREG(MODR),
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.drcmr = &DRCMRRXMODR,
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.drcmr = &DRCMR(9),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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@ -276,7 +276,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
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.name = "AC97 Mic PCM (Slot 6) Mono in",
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.dev_addr = __PREG(MCDR),
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.drcmr = &DRCMRRXMCDR,
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||||
.drcmr = &DRCMR(8),
|
||||
.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
|
||||
DCMD_BURST16 | DCMD_WIDTH2,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ static struct clk *clk_i2s;
|
|||
static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
|
||||
.name = "I2S PCM Stereo out",
|
||||
.dev_addr = __PREG(SADR),
|
||||
.drcmr = &DRCMRTXSADR,
|
||||
.drcmr = &DRCMR(3),
|
||||
.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
|
||||
DCMD_BURST32 | DCMD_WIDTH4,
|
||||
};
|
||||
|
|
@ -52,7 +52,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
|
|||
static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
|
||||
.name = "I2S PCM Stereo in",
|
||||
.dev_addr = __PREG(SADR),
|
||||
.drcmr = &DRCMRRXSADR,
|
||||
.drcmr = &DRCMR(2),
|
||||
.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
|
||||
DCMD_BURST32 | DCMD_WIDTH4,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue