mirror of https://gitee.com/openkylin/linux.git
KVM: SVM: Move Nested SVM Implementation to nested.c
Split out the code for the nested SVM implementation and move it to a separate file. Signed-off-by: Joerg Roedel <jroedel@suse.de> Message-Id: <20200324094154.32352-3-joro@8bytes.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Joerg Roedel
Paolo Bonzini
parent
46a010dd68
commit
883b0a91f4
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@ -14,7 +14,7 @@ kvm-y += x86.o emulate.o i8259.o irq.o lapic.o \
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hyperv.o debugfs.o mmu/mmu.o mmu/page_track.o
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kvm-intel-y += vmx/vmx.o vmx/vmenter.o vmx/pmu_intel.o vmx/vmcs12.o vmx/evmcs.o vmx/nested.o
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kvm-amd-y += svm/svm.o svm/pmu.o
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kvm-amd-y += svm/svm.o svm/pmu.o svm/nested.o
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obj-$(CONFIG_KVM) += kvm.o
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obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
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@ -0,0 +1,823 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Kernel-based Virtual Machine driver for Linux
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*
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* AMD SVM support
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*
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* Copyright (C) 2006 Qumranet, Inc.
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Yaniv Kamay <yaniv@qumranet.com>
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* Avi Kivity <avi@qumranet.com>
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*/
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#define pr_fmt(fmt) "SVM: " fmt
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#include <linux/kvm_types.h>
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#include <linux/kvm_host.h>
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#include <linux/kernel.h>
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#include <asm/msr-index.h>
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#include "kvm_emulate.h"
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#include "trace.h"
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#include "mmu.h"
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#include "x86.h"
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#include "svm.h"
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static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
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struct x86_exception *fault)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
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/*
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* TODO: track the cause of the nested page fault, and
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* correctly fill in the high bits of exit_info_1.
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*/
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svm->vmcb->control.exit_code = SVM_EXIT_NPF;
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svm->vmcb->control.exit_code_hi = 0;
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svm->vmcb->control.exit_info_1 = (1ULL << 32);
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svm->vmcb->control.exit_info_2 = fault->address;
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}
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svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
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svm->vmcb->control.exit_info_1 |= fault->error_code;
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/*
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* The present bit is always zero for page structure faults on real
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* hardware.
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*/
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if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
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svm->vmcb->control.exit_info_1 &= ~1;
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nested_svm_vmexit(svm);
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}
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static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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u64 cr3 = svm->nested.nested_cr3;
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u64 pdpte;
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int ret;
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ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
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offset_in_page(cr3) + index * 8, 8);
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if (ret)
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return 0;
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return pdpte;
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}
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static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
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{
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struct vcpu_svm *svm = to_svm(vcpu);
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return svm->nested.nested_cr3;
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}
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static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
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{
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WARN_ON(mmu_is_nested(vcpu));
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vcpu->arch.mmu = &vcpu->arch.guest_mmu;
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kvm_init_shadow_mmu(vcpu);
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vcpu->arch.mmu->get_guest_pgd = nested_svm_get_tdp_cr3;
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vcpu->arch.mmu->get_pdptr = nested_svm_get_tdp_pdptr;
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vcpu->arch.mmu->inject_page_fault = nested_svm_inject_npf_exit;
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vcpu->arch.mmu->shadow_root_level = kvm_x86_ops.get_tdp_level(vcpu);
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reset_shadow_zero_bits_mask(vcpu, vcpu->arch.mmu);
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vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
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}
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static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.mmu = &vcpu->arch.root_mmu;
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vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
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}
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void recalc_intercepts(struct vcpu_svm *svm)
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{
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struct vmcb_control_area *c, *h;
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struct nested_state *g;
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mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
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if (!is_guest_mode(&svm->vcpu))
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return;
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c = &svm->vmcb->control;
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h = &svm->nested.hsave->control;
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g = &svm->nested;
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c->intercept_cr = h->intercept_cr;
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c->intercept_dr = h->intercept_dr;
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c->intercept_exceptions = h->intercept_exceptions;
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c->intercept = h->intercept;
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if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
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/* We only want the cr8 intercept bits of L1 */
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c->intercept_cr &= ~(1U << INTERCEPT_CR8_READ);
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c->intercept_cr &= ~(1U << INTERCEPT_CR8_WRITE);
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/*
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* Once running L2 with HF_VINTR_MASK, EFLAGS.IF does not
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* affect any interrupt we may want to inject; therefore,
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* interrupt window vmexits are irrelevant to L0.
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*/
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c->intercept &= ~(1ULL << INTERCEPT_VINTR);
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}
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/* We don't want to see VMMCALLs from a nested guest */
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c->intercept &= ~(1ULL << INTERCEPT_VMMCALL);
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c->intercept_cr |= g->intercept_cr;
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c->intercept_dr |= g->intercept_dr;
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c->intercept_exceptions |= g->intercept_exceptions;
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c->intercept |= g->intercept;
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}
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static void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
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{
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struct vmcb_control_area *dst = &dst_vmcb->control;
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struct vmcb_control_area *from = &from_vmcb->control;
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dst->intercept_cr = from->intercept_cr;
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dst->intercept_dr = from->intercept_dr;
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dst->intercept_exceptions = from->intercept_exceptions;
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dst->intercept = from->intercept;
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dst->iopm_base_pa = from->iopm_base_pa;
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dst->msrpm_base_pa = from->msrpm_base_pa;
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dst->tsc_offset = from->tsc_offset;
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dst->asid = from->asid;
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dst->tlb_ctl = from->tlb_ctl;
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dst->int_ctl = from->int_ctl;
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dst->int_vector = from->int_vector;
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dst->int_state = from->int_state;
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dst->exit_code = from->exit_code;
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dst->exit_code_hi = from->exit_code_hi;
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dst->exit_info_1 = from->exit_info_1;
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dst->exit_info_2 = from->exit_info_2;
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dst->exit_int_info = from->exit_int_info;
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dst->exit_int_info_err = from->exit_int_info_err;
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dst->nested_ctl = from->nested_ctl;
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dst->event_inj = from->event_inj;
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dst->event_inj_err = from->event_inj_err;
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dst->nested_cr3 = from->nested_cr3;
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dst->virt_ext = from->virt_ext;
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dst->pause_filter_count = from->pause_filter_count;
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dst->pause_filter_thresh = from->pause_filter_thresh;
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}
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static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
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{
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/*
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* This function merges the msr permission bitmaps of kvm and the
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* nested vmcb. It is optimized in that it only merges the parts where
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* the kvm msr permission bitmap may contain zero bits
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*/
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int i;
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if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
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return true;
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for (i = 0; i < MSRPM_OFFSETS; i++) {
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u32 value, p;
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u64 offset;
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if (msrpm_offsets[i] == 0xffffffff)
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break;
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p = msrpm_offsets[i];
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offset = svm->nested.vmcb_msrpm + (p * 4);
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if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
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return false;
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svm->nested.msrpm[p] = svm->msrpm[p] | value;
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}
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svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
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return true;
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}
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static bool nested_vmcb_checks(struct vmcb *vmcb)
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{
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if ((vmcb->save.efer & EFER_SVME) == 0)
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return false;
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if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
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return false;
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if (vmcb->control.asid == 0)
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return false;
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if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
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!npt_enabled)
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return false;
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return true;
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}
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void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
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struct vmcb *nested_vmcb, struct kvm_host_map *map)
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{
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bool evaluate_pending_interrupts =
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is_intercept(svm, INTERCEPT_VINTR) ||
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is_intercept(svm, INTERCEPT_IRET);
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if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
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svm->vcpu.arch.hflags |= HF_HIF_MASK;
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else
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svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
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if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
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svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
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nested_svm_init_mmu_context(&svm->vcpu);
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}
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/* Load the nested guest state */
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svm->vmcb->save.es = nested_vmcb->save.es;
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svm->vmcb->save.cs = nested_vmcb->save.cs;
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svm->vmcb->save.ss = nested_vmcb->save.ss;
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svm->vmcb->save.ds = nested_vmcb->save.ds;
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svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
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svm->vmcb->save.idtr = nested_vmcb->save.idtr;
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kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
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svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
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svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
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svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
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if (npt_enabled) {
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svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
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svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
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} else
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(void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
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/* Guest paging mode is active - reset mmu */
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kvm_mmu_reset_context(&svm->vcpu);
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svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
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kvm_rax_write(&svm->vcpu, nested_vmcb->save.rax);
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kvm_rsp_write(&svm->vcpu, nested_vmcb->save.rsp);
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kvm_rip_write(&svm->vcpu, nested_vmcb->save.rip);
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/* In case we don't even reach vcpu_run, the fields are not updated */
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svm->vmcb->save.rax = nested_vmcb->save.rax;
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svm->vmcb->save.rsp = nested_vmcb->save.rsp;
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svm->vmcb->save.rip = nested_vmcb->save.rip;
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svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
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svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
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svm->vmcb->save.cpl = nested_vmcb->save.cpl;
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svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
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svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
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/* cache intercepts */
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svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
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svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
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svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
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svm->nested.intercept = nested_vmcb->control.intercept;
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svm_flush_tlb(&svm->vcpu, true);
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svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
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if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
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svm->vcpu.arch.hflags |= HF_VINTR_MASK;
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else
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svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
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svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
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svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
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svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
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svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
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svm->vmcb->control.int_state = nested_vmcb->control.int_state;
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svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
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svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
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svm->vmcb->control.pause_filter_count =
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nested_vmcb->control.pause_filter_count;
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svm->vmcb->control.pause_filter_thresh =
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nested_vmcb->control.pause_filter_thresh;
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kvm_vcpu_unmap(&svm->vcpu, map, true);
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/* Enter Guest-Mode */
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enter_guest_mode(&svm->vcpu);
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/*
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* Merge guest and host intercepts - must be called with vcpu in
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* guest-mode to take affect here
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*/
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recalc_intercepts(svm);
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svm->nested.vmcb = vmcb_gpa;
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/*
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* If L1 had a pending IRQ/NMI before executing VMRUN,
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* which wasn't delivered because it was disallowed (e.g.
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* interrupts disabled), L0 needs to evaluate if this pending
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* event should cause an exit from L2 to L1 or be delivered
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* directly to L2.
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*
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* Usually this would be handled by the processor noticing an
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* IRQ/NMI window request. However, VMRUN can unblock interrupts
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* by implicitly setting GIF, so force L0 to perform pending event
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* evaluation by requesting a KVM_REQ_EVENT.
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*/
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enable_gif(svm);
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if (unlikely(evaluate_pending_interrupts))
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kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
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mark_all_dirty(svm->vmcb);
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}
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int nested_svm_vmrun(struct vcpu_svm *svm)
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{
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int ret;
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struct vmcb *nested_vmcb;
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struct vmcb *hsave = svm->nested.hsave;
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struct vmcb *vmcb = svm->vmcb;
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struct kvm_host_map map;
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u64 vmcb_gpa;
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vmcb_gpa = svm->vmcb->save.rax;
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ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb_gpa), &map);
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if (ret == -EINVAL) {
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kvm_inject_gp(&svm->vcpu, 0);
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return 1;
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} else if (ret) {
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return kvm_skip_emulated_instruction(&svm->vcpu);
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}
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ret = kvm_skip_emulated_instruction(&svm->vcpu);
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nested_vmcb = map.hva;
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if (!nested_vmcb_checks(nested_vmcb)) {
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nested_vmcb->control.exit_code = SVM_EXIT_ERR;
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nested_vmcb->control.exit_code_hi = 0;
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nested_vmcb->control.exit_info_1 = 0;
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nested_vmcb->control.exit_info_2 = 0;
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kvm_vcpu_unmap(&svm->vcpu, &map, true);
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return ret;
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}
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trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
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nested_vmcb->save.rip,
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nested_vmcb->control.int_ctl,
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nested_vmcb->control.event_inj,
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nested_vmcb->control.nested_ctl);
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trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
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nested_vmcb->control.intercept_cr >> 16,
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nested_vmcb->control.intercept_exceptions,
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nested_vmcb->control.intercept);
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/* Clear internal status */
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kvm_clear_exception_queue(&svm->vcpu);
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kvm_clear_interrupt_queue(&svm->vcpu);
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/*
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* Save the old vmcb, so we don't need to pick what we save, but can
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* restore everything when a VMEXIT occurs
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*/
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hsave->save.es = vmcb->save.es;
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hsave->save.cs = vmcb->save.cs;
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hsave->save.ss = vmcb->save.ss;
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hsave->save.ds = vmcb->save.ds;
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hsave->save.gdtr = vmcb->save.gdtr;
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hsave->save.idtr = vmcb->save.idtr;
|
||||
hsave->save.efer = svm->vcpu.arch.efer;
|
||||
hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
|
||||
hsave->save.cr4 = svm->vcpu.arch.cr4;
|
||||
hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
|
||||
hsave->save.rip = kvm_rip_read(&svm->vcpu);
|
||||
hsave->save.rsp = vmcb->save.rsp;
|
||||
hsave->save.rax = vmcb->save.rax;
|
||||
if (npt_enabled)
|
||||
hsave->save.cr3 = vmcb->save.cr3;
|
||||
else
|
||||
hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
|
||||
|
||||
copy_vmcb_control_area(hsave, vmcb);
|
||||
|
||||
enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, &map);
|
||||
|
||||
if (!nested_svm_vmrun_msrpm(svm)) {
|
||||
svm->vmcb->control.exit_code = SVM_EXIT_ERR;
|
||||
svm->vmcb->control.exit_code_hi = 0;
|
||||
svm->vmcb->control.exit_info_1 = 0;
|
||||
svm->vmcb->control.exit_info_2 = 0;
|
||||
|
||||
nested_svm_vmexit(svm);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
|
||||
{
|
||||
to_vmcb->save.fs = from_vmcb->save.fs;
|
||||
to_vmcb->save.gs = from_vmcb->save.gs;
|
||||
to_vmcb->save.tr = from_vmcb->save.tr;
|
||||
to_vmcb->save.ldtr = from_vmcb->save.ldtr;
|
||||
to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
|
||||
to_vmcb->save.star = from_vmcb->save.star;
|
||||
to_vmcb->save.lstar = from_vmcb->save.lstar;
|
||||
to_vmcb->save.cstar = from_vmcb->save.cstar;
|
||||
to_vmcb->save.sfmask = from_vmcb->save.sfmask;
|
||||
to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
|
||||
to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
|
||||
to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
|
||||
}
|
||||
|
||||
int nested_svm_vmexit(struct vcpu_svm *svm)
|
||||
{
|
||||
int rc;
|
||||
struct vmcb *nested_vmcb;
|
||||
struct vmcb *hsave = svm->nested.hsave;
|
||||
struct vmcb *vmcb = svm->vmcb;
|
||||
struct kvm_host_map map;
|
||||
|
||||
trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
|
||||
vmcb->control.exit_info_1,
|
||||
vmcb->control.exit_info_2,
|
||||
vmcb->control.exit_int_info,
|
||||
vmcb->control.exit_int_info_err,
|
||||
KVM_ISA_SVM);
|
||||
|
||||
rc = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->nested.vmcb), &map);
|
||||
if (rc) {
|
||||
if (rc == -EINVAL)
|
||||
kvm_inject_gp(&svm->vcpu, 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
nested_vmcb = map.hva;
|
||||
|
||||
/* Exit Guest-Mode */
|
||||
leave_guest_mode(&svm->vcpu);
|
||||
svm->nested.vmcb = 0;
|
||||
|
||||
/* Give the current vmcb to the guest */
|
||||
disable_gif(svm);
|
||||
|
||||
nested_vmcb->save.es = vmcb->save.es;
|
||||
nested_vmcb->save.cs = vmcb->save.cs;
|
||||
nested_vmcb->save.ss = vmcb->save.ss;
|
||||
nested_vmcb->save.ds = vmcb->save.ds;
|
||||
nested_vmcb->save.gdtr = vmcb->save.gdtr;
|
||||
nested_vmcb->save.idtr = vmcb->save.idtr;
|
||||
nested_vmcb->save.efer = svm->vcpu.arch.efer;
|
||||
nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
|
||||
nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
|
||||
nested_vmcb->save.cr2 = vmcb->save.cr2;
|
||||
nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
|
||||
nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
|
||||
nested_vmcb->save.rip = vmcb->save.rip;
|
||||
nested_vmcb->save.rsp = vmcb->save.rsp;
|
||||
nested_vmcb->save.rax = vmcb->save.rax;
|
||||
nested_vmcb->save.dr7 = vmcb->save.dr7;
|
||||
nested_vmcb->save.dr6 = vmcb->save.dr6;
|
||||
nested_vmcb->save.cpl = vmcb->save.cpl;
|
||||
|
||||
nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
|
||||
nested_vmcb->control.int_vector = vmcb->control.int_vector;
|
||||
nested_vmcb->control.int_state = vmcb->control.int_state;
|
||||
nested_vmcb->control.exit_code = vmcb->control.exit_code;
|
||||
nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
|
||||
nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
|
||||
nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
|
||||
nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
|
||||
nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
|
||||
|
||||
if (svm->nrips_enabled)
|
||||
nested_vmcb->control.next_rip = vmcb->control.next_rip;
|
||||
|
||||
/*
|
||||
* If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
|
||||
* to make sure that we do not lose injected events. So check event_inj
|
||||
* here and copy it to exit_int_info if it is valid.
|
||||
* Exit_int_info and event_inj can't be both valid because the case
|
||||
* below only happens on a VMRUN instruction intercept which has
|
||||
* no valid exit_int_info set.
|
||||
*/
|
||||
if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
|
||||
struct vmcb_control_area *nc = &nested_vmcb->control;
|
||||
|
||||
nc->exit_int_info = vmcb->control.event_inj;
|
||||
nc->exit_int_info_err = vmcb->control.event_inj_err;
|
||||
}
|
||||
|
||||
nested_vmcb->control.tlb_ctl = 0;
|
||||
nested_vmcb->control.event_inj = 0;
|
||||
nested_vmcb->control.event_inj_err = 0;
|
||||
|
||||
nested_vmcb->control.pause_filter_count =
|
||||
svm->vmcb->control.pause_filter_count;
|
||||
nested_vmcb->control.pause_filter_thresh =
|
||||
svm->vmcb->control.pause_filter_thresh;
|
||||
|
||||
/* We always set V_INTR_MASKING and remember the old value in hflags */
|
||||
if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
|
||||
nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
|
||||
|
||||
/* Restore the original control entries */
|
||||
copy_vmcb_control_area(vmcb, hsave);
|
||||
|
||||
svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
|
||||
kvm_clear_exception_queue(&svm->vcpu);
|
||||
kvm_clear_interrupt_queue(&svm->vcpu);
|
||||
|
||||
svm->nested.nested_cr3 = 0;
|
||||
|
||||
/* Restore selected save entries */
|
||||
svm->vmcb->save.es = hsave->save.es;
|
||||
svm->vmcb->save.cs = hsave->save.cs;
|
||||
svm->vmcb->save.ss = hsave->save.ss;
|
||||
svm->vmcb->save.ds = hsave->save.ds;
|
||||
svm->vmcb->save.gdtr = hsave->save.gdtr;
|
||||
svm->vmcb->save.idtr = hsave->save.idtr;
|
||||
kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
|
||||
svm_set_efer(&svm->vcpu, hsave->save.efer);
|
||||
svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
|
||||
svm_set_cr4(&svm->vcpu, hsave->save.cr4);
|
||||
if (npt_enabled) {
|
||||
svm->vmcb->save.cr3 = hsave->save.cr3;
|
||||
svm->vcpu.arch.cr3 = hsave->save.cr3;
|
||||
} else {
|
||||
(void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
|
||||
}
|
||||
kvm_rax_write(&svm->vcpu, hsave->save.rax);
|
||||
kvm_rsp_write(&svm->vcpu, hsave->save.rsp);
|
||||
kvm_rip_write(&svm->vcpu, hsave->save.rip);
|
||||
svm->vmcb->save.dr7 = 0;
|
||||
svm->vmcb->save.cpl = 0;
|
||||
svm->vmcb->control.exit_int_info = 0;
|
||||
|
||||
mark_all_dirty(svm->vmcb);
|
||||
|
||||
kvm_vcpu_unmap(&svm->vcpu, &map, true);
|
||||
|
||||
nested_svm_uninit_mmu_context(&svm->vcpu);
|
||||
kvm_mmu_reset_context(&svm->vcpu);
|
||||
kvm_mmu_load(&svm->vcpu);
|
||||
|
||||
/*
|
||||
* Drop what we picked up for L2 via svm_complete_interrupts() so it
|
||||
* doesn't end up in L1.
|
||||
*/
|
||||
svm->vcpu.arch.nmi_injected = false;
|
||||
kvm_clear_exception_queue(&svm->vcpu);
|
||||
kvm_clear_interrupt_queue(&svm->vcpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
|
||||
{
|
||||
u32 offset, msr, value;
|
||||
int write, mask;
|
||||
|
||||
if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
|
||||
return NESTED_EXIT_HOST;
|
||||
|
||||
msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
|
||||
offset = svm_msrpm_offset(msr);
|
||||
write = svm->vmcb->control.exit_info_1 & 1;
|
||||
mask = 1 << ((2 * (msr & 0xf)) + write);
|
||||
|
||||
if (offset == MSR_INVALID)
|
||||
return NESTED_EXIT_DONE;
|
||||
|
||||
/* Offset is in 32 bit units but need in 8 bit units */
|
||||
offset *= 4;
|
||||
|
||||
if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
|
||||
return NESTED_EXIT_DONE;
|
||||
|
||||
return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
|
||||
}
|
||||
|
||||
/* DB exceptions for our internal use must not cause vmexit */
|
||||
static int nested_svm_intercept_db(struct vcpu_svm *svm)
|
||||
{
|
||||
unsigned long dr6;
|
||||
|
||||
/* if we're not singlestepping, it's not ours */
|
||||
if (!svm->nmi_singlestep)
|
||||
return NESTED_EXIT_DONE;
|
||||
|
||||
/* if it's not a singlestep exception, it's not ours */
|
||||
if (kvm_get_dr(&svm->vcpu, 6, &dr6))
|
||||
return NESTED_EXIT_DONE;
|
||||
if (!(dr6 & DR6_BS))
|
||||
return NESTED_EXIT_DONE;
|
||||
|
||||
/* if the guest is singlestepping, it should get the vmexit */
|
||||
if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
|
||||
disable_nmi_singlestep(svm);
|
||||
return NESTED_EXIT_DONE;
|
||||
}
|
||||
|
||||
/* it's ours, the nested hypervisor must not see this one */
|
||||
return NESTED_EXIT_HOST;
|
||||
}
|
||||
|
||||
static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
|
||||
{
|
||||
unsigned port, size, iopm_len;
|
||||
u16 val, mask;
|
||||
u8 start_bit;
|
||||
u64 gpa;
|
||||
|
||||
if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
|
||||
return NESTED_EXIT_HOST;
|
||||
|
||||
port = svm->vmcb->control.exit_info_1 >> 16;
|
||||
size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
|
||||
SVM_IOIO_SIZE_SHIFT;
|
||||
gpa = svm->nested.vmcb_iopm + (port / 8);
|
||||
start_bit = port % 8;
|
||||
iopm_len = (start_bit + size > 8) ? 2 : 1;
|
||||
mask = (0xf >> (4 - size)) << start_bit;
|
||||
val = 0;
|
||||
|
||||
if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
|
||||
return NESTED_EXIT_DONE;
|
||||
|
||||
return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
|
||||
}
|
||||
|
||||
static int nested_svm_intercept(struct vcpu_svm *svm)
|
||||
{
|
||||
u32 exit_code = svm->vmcb->control.exit_code;
|
||||
int vmexit = NESTED_EXIT_HOST;
|
||||
|
||||
switch (exit_code) {
|
||||
case SVM_EXIT_MSR:
|
||||
vmexit = nested_svm_exit_handled_msr(svm);
|
||||
break;
|
||||
case SVM_EXIT_IOIO:
|
||||
vmexit = nested_svm_intercept_ioio(svm);
|
||||
break;
|
||||
case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
|
||||
u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
|
||||
if (svm->nested.intercept_cr & bit)
|
||||
vmexit = NESTED_EXIT_DONE;
|
||||
break;
|
||||
}
|
||||
case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
|
||||
u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
|
||||
if (svm->nested.intercept_dr & bit)
|
||||
vmexit = NESTED_EXIT_DONE;
|
||||
break;
|
||||
}
|
||||
case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
|
||||
u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
|
||||
if (svm->nested.intercept_exceptions & excp_bits) {
|
||||
if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
|
||||
vmexit = nested_svm_intercept_db(svm);
|
||||
else
|
||||
vmexit = NESTED_EXIT_DONE;
|
||||
}
|
||||
/* async page fault always cause vmexit */
|
||||
else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
|
||||
svm->vcpu.arch.exception.nested_apf != 0)
|
||||
vmexit = NESTED_EXIT_DONE;
|
||||
break;
|
||||
}
|
||||
case SVM_EXIT_ERR: {
|
||||
vmexit = NESTED_EXIT_DONE;
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
|
||||
if (svm->nested.intercept & exit_bits)
|
||||
vmexit = NESTED_EXIT_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
return vmexit;
|
||||
}
|
||||
|
||||
int nested_svm_exit_handled(struct vcpu_svm *svm)
|
||||
{
|
||||
int vmexit;
|
||||
|
||||
vmexit = nested_svm_intercept(svm);
|
||||
|
||||
if (vmexit == NESTED_EXIT_DONE)
|
||||
nested_svm_vmexit(svm);
|
||||
|
||||
return vmexit;
|
||||
}
|
||||
|
||||
int nested_svm_check_permissions(struct vcpu_svm *svm)
|
||||
{
|
||||
if (!(svm->vcpu.arch.efer & EFER_SVME) ||
|
||||
!is_paging(&svm->vcpu)) {
|
||||
kvm_queue_exception(&svm->vcpu, UD_VECTOR);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (svm->vmcb->save.cpl) {
|
||||
kvm_inject_gp(&svm->vcpu, 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
|
||||
bool has_error_code, u32 error_code)
|
||||
{
|
||||
int vmexit;
|
||||
|
||||
if (!is_guest_mode(&svm->vcpu))
|
||||
return 0;
|
||||
|
||||
vmexit = nested_svm_intercept(svm);
|
||||
if (vmexit != NESTED_EXIT_DONE)
|
||||
return 0;
|
||||
|
||||
svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
|
||||
svm->vmcb->control.exit_code_hi = 0;
|
||||
svm->vmcb->control.exit_info_1 = error_code;
|
||||
|
||||
/*
|
||||
* EXITINFO2 is undefined for all exception intercepts other
|
||||
* than #PF.
|
||||
*/
|
||||
if (svm->vcpu.arch.exception.nested_apf)
|
||||
svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
|
||||
else if (svm->vcpu.arch.exception.has_payload)
|
||||
svm->vmcb->control.exit_info_2 = svm->vcpu.arch.exception.payload;
|
||||
else
|
||||
svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
|
||||
|
||||
svm->nested.exit_required = true;
|
||||
return vmexit;
|
||||
}
|
||||
|
||||
static void nested_svm_intr(struct vcpu_svm *svm)
|
||||
{
|
||||
svm->vmcb->control.exit_code = SVM_EXIT_INTR;
|
||||
svm->vmcb->control.exit_info_1 = 0;
|
||||
svm->vmcb->control.exit_info_2 = 0;
|
||||
|
||||
/* nested_svm_vmexit this gets called afterwards from handle_exit */
|
||||
svm->nested.exit_required = true;
|
||||
trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
|
||||
}
|
||||
|
||||
static bool nested_exit_on_intr(struct vcpu_svm *svm)
|
||||
{
|
||||
return (svm->nested.intercept & 1ULL);
|
||||
}
|
||||
|
||||
int svm_check_nested_events(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct vcpu_svm *svm = to_svm(vcpu);
|
||||
bool block_nested_events =
|
||||
kvm_event_needs_reinjection(vcpu) || svm->nested.exit_required;
|
||||
|
||||
if (kvm_cpu_has_interrupt(vcpu) && nested_exit_on_intr(svm)) {
|
||||
if (block_nested_events)
|
||||
return -EBUSY;
|
||||
nested_svm_intr(svm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nested_svm_exit_special(struct vcpu_svm *svm)
|
||||
{
|
||||
u32 exit_code = svm->vmcb->control.exit_code;
|
||||
|
||||
switch (exit_code) {
|
||||
case SVM_EXIT_INTR:
|
||||
case SVM_EXIT_NMI:
|
||||
case SVM_EXIT_EXCP_BASE + MC_VECTOR:
|
||||
return NESTED_EXIT_HOST;
|
||||
case SVM_EXIT_NPF:
|
||||
/* For now we are always handling NPFs when using them */
|
||||
if (npt_enabled)
|
||||
return NESTED_EXIT_HOST;
|
||||
break;
|
||||
case SVM_EXIT_EXCP_BASE + PF_VECTOR:
|
||||
/* When we're shadowing, trap PFs, but not async PF */
|
||||
if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
|
||||
return NESTED_EXIT_HOST;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return NESTED_EXIT_CONTINUE;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,381 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Kernel-based Virtual Machine driver for Linux
|
||||
*
|
||||
* AMD SVM support
|
||||
*
|
||||
* Copyright (C) 2006 Qumranet, Inc.
|
||||
* Copyright 2010 Red Hat, Inc. and/or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Yaniv Kamay <yaniv@qumranet.com>
|
||||
* Avi Kivity <avi@qumranet.com>
|
||||
*/
|
||||
|
||||
#ifndef __SVM_SVM_H
|
||||
#define __SVM_SVM_H
|
||||
|
||||
#include <linux/kvm_types.h>
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
#include <asm/svm.h>
|
||||
|
||||
static const u32 host_save_user_msrs[] = {
|
||||
#ifdef CONFIG_X86_64
|
||||
MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
|
||||
MSR_FS_BASE,
|
||||
#endif
|
||||
MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
|
||||
MSR_TSC_AUX,
|
||||
};
|
||||
|
||||
#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
|
||||
|
||||
#define MSRPM_OFFSETS 16
|
||||
extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
|
||||
extern bool npt_enabled;
|
||||
|
||||
enum {
|
||||
VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
|
||||
pause filter count */
|
||||
VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
|
||||
VMCB_ASID, /* ASID */
|
||||
VMCB_INTR, /* int_ctl, int_vector */
|
||||
VMCB_NPT, /* npt_en, nCR3, gPAT */
|
||||
VMCB_CR, /* CR0, CR3, CR4, EFER */
|
||||
VMCB_DR, /* DR6, DR7 */
|
||||
VMCB_DT, /* GDT, IDT */
|
||||
VMCB_SEG, /* CS, DS, SS, ES, CPL */
|
||||
VMCB_CR2, /* CR2 only */
|
||||
VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
|
||||
VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
|
||||
* AVIC PHYSICAL_TABLE pointer,
|
||||
* AVIC LOGICAL_TABLE pointer
|
||||
*/
|
||||
VMCB_DIRTY_MAX,
|
||||
};
|
||||
|
||||
/* TPR and CR2 are always written before VMRUN */
|
||||
#define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
|
||||
|
||||
struct kvm_sev_info {
|
||||
bool active; /* SEV enabled guest */
|
||||
unsigned int asid; /* ASID used for this guest */
|
||||
unsigned int handle; /* SEV firmware handle */
|
||||
int fd; /* SEV device fd */
|
||||
unsigned long pages_locked; /* Number of pages locked */
|
||||
struct list_head regions_list; /* List of registered regions */
|
||||
};
|
||||
|
||||
struct kvm_svm {
|
||||
struct kvm kvm;
|
||||
|
||||
/* Struct members for AVIC */
|
||||
u32 avic_vm_id;
|
||||
struct page *avic_logical_id_table_page;
|
||||
struct page *avic_physical_id_table_page;
|
||||
struct hlist_node hnode;
|
||||
|
||||
struct kvm_sev_info sev_info;
|
||||
};
|
||||
|
||||
struct kvm_vcpu;
|
||||
|
||||
struct nested_state {
|
||||
struct vmcb *hsave;
|
||||
u64 hsave_msr;
|
||||
u64 vm_cr_msr;
|
||||
u64 vmcb;
|
||||
|
||||
/* These are the merged vectors */
|
||||
u32 *msrpm;
|
||||
|
||||
/* gpa pointers to the real vectors */
|
||||
u64 vmcb_msrpm;
|
||||
u64 vmcb_iopm;
|
||||
|
||||
/* A VMEXIT is required but not yet emulated */
|
||||
bool exit_required;
|
||||
|
||||
/* cache for intercepts of the guest */
|
||||
u32 intercept_cr;
|
||||
u32 intercept_dr;
|
||||
u32 intercept_exceptions;
|
||||
u64 intercept;
|
||||
|
||||
/* Nested Paging related state */
|
||||
u64 nested_cr3;
|
||||
};
|
||||
|
||||
struct vcpu_svm {
|
||||
struct kvm_vcpu vcpu;
|
||||
struct vmcb *vmcb;
|
||||
unsigned long vmcb_pa;
|
||||
struct svm_cpu_data *svm_data;
|
||||
uint64_t asid_generation;
|
||||
uint64_t sysenter_esp;
|
||||
uint64_t sysenter_eip;
|
||||
uint64_t tsc_aux;
|
||||
|
||||
u64 msr_decfg;
|
||||
|
||||
u64 next_rip;
|
||||
|
||||
u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
|
||||
struct {
|
||||
u16 fs;
|
||||
u16 gs;
|
||||
u16 ldt;
|
||||
u64 gs_base;
|
||||
} host;
|
||||
|
||||
u64 spec_ctrl;
|
||||
/*
|
||||
* Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
|
||||
* translated into the appropriate L2_CFG bits on the host to
|
||||
* perform speculative control.
|
||||
*/
|
||||
u64 virt_spec_ctrl;
|
||||
|
||||
u32 *msrpm;
|
||||
|
||||
ulong nmi_iret_rip;
|
||||
|
||||
struct nested_state nested;
|
||||
|
||||
bool nmi_singlestep;
|
||||
u64 nmi_singlestep_guest_rflags;
|
||||
|
||||
unsigned int3_injected;
|
||||
unsigned long int3_rip;
|
||||
|
||||
/* cached guest cpuid flags for faster access */
|
||||
bool nrips_enabled : 1;
|
||||
|
||||
u32 ldr_reg;
|
||||
u32 dfr_reg;
|
||||
struct page *avic_backing_page;
|
||||
u64 *avic_physical_id_cache;
|
||||
bool avic_is_running;
|
||||
|
||||
/*
|
||||
* Per-vcpu list of struct amd_svm_iommu_ir:
|
||||
* This is used mainly to store interrupt remapping information used
|
||||
* when update the vcpu affinity. This avoids the need to scan for
|
||||
* IRTE and try to match ga_tag in the IOMMU driver.
|
||||
*/
|
||||
struct list_head ir_list;
|
||||
spinlock_t ir_list_lock;
|
||||
|
||||
/* which host CPU was used for running this vcpu */
|
||||
unsigned int last_cpu;
|
||||
};
|
||||
|
||||
void recalc_intercepts(struct vcpu_svm *svm);
|
||||
|
||||
static inline void mark_all_dirty(struct vmcb *vmcb)
|
||||
{
|
||||
vmcb->control.clean = 0;
|
||||
}
|
||||
|
||||
static inline void mark_all_clean(struct vmcb *vmcb)
|
||||
{
|
||||
vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
|
||||
& ~VMCB_ALWAYS_DIRTY_MASK;
|
||||
}
|
||||
|
||||
static inline void mark_dirty(struct vmcb *vmcb, int bit)
|
||||
{
|
||||
vmcb->control.clean &= ~(1 << bit);
|
||||
}
|
||||
|
||||
static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return container_of(vcpu, struct vcpu_svm, vcpu);
|
||||
}
|
||||
|
||||
static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
|
||||
{
|
||||
if (is_guest_mode(&svm->vcpu))
|
||||
return svm->nested.hsave;
|
||||
else
|
||||
return svm->vmcb;
|
||||
}
|
||||
|
||||
static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept_cr |= (1U << bit);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept_cr &= ~(1U << bit);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
return vmcb->control.intercept_cr & (1U << bit);
|
||||
}
|
||||
|
||||
static inline void set_dr_intercepts(struct vcpu_svm *svm)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
|
||||
| (1 << INTERCEPT_DR1_READ)
|
||||
| (1 << INTERCEPT_DR2_READ)
|
||||
| (1 << INTERCEPT_DR3_READ)
|
||||
| (1 << INTERCEPT_DR4_READ)
|
||||
| (1 << INTERCEPT_DR5_READ)
|
||||
| (1 << INTERCEPT_DR6_READ)
|
||||
| (1 << INTERCEPT_DR7_READ)
|
||||
| (1 << INTERCEPT_DR0_WRITE)
|
||||
| (1 << INTERCEPT_DR1_WRITE)
|
||||
| (1 << INTERCEPT_DR2_WRITE)
|
||||
| (1 << INTERCEPT_DR3_WRITE)
|
||||
| (1 << INTERCEPT_DR4_WRITE)
|
||||
| (1 << INTERCEPT_DR5_WRITE)
|
||||
| (1 << INTERCEPT_DR6_WRITE)
|
||||
| (1 << INTERCEPT_DR7_WRITE);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline void clr_dr_intercepts(struct vcpu_svm *svm)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept_dr = 0;
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept_exceptions |= (1U << bit);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept_exceptions &= ~(1U << bit);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline void set_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept |= (1ULL << bit);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline void clr_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
struct vmcb *vmcb = get_host_vmcb(svm);
|
||||
|
||||
vmcb->control.intercept &= ~(1ULL << bit);
|
||||
|
||||
recalc_intercepts(svm);
|
||||
}
|
||||
|
||||
static inline bool is_intercept(struct vcpu_svm *svm, int bit)
|
||||
{
|
||||
return (svm->vmcb->control.intercept & (1ULL << bit)) != 0;
|
||||
}
|
||||
|
||||
static inline bool vgif_enabled(struct vcpu_svm *svm)
|
||||
{
|
||||
return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
|
||||
}
|
||||
|
||||
static inline void enable_gif(struct vcpu_svm *svm)
|
||||
{
|
||||
if (vgif_enabled(svm))
|
||||
svm->vmcb->control.int_ctl |= V_GIF_MASK;
|
||||
else
|
||||
svm->vcpu.arch.hflags |= HF_GIF_MASK;
|
||||
}
|
||||
|
||||
static inline void disable_gif(struct vcpu_svm *svm)
|
||||
{
|
||||
if (vgif_enabled(svm))
|
||||
svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
|
||||
else
|
||||
svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
|
||||
}
|
||||
|
||||
static inline bool gif_set(struct vcpu_svm *svm)
|
||||
{
|
||||
if (vgif_enabled(svm))
|
||||
return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
|
||||
else
|
||||
return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
|
||||
}
|
||||
|
||||
/* svm.c */
|
||||
#define MSR_INVALID 0xffffffffU
|
||||
|
||||
u32 svm_msrpm_offset(u32 msr);
|
||||
void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
|
||||
void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
|
||||
int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
|
||||
void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
|
||||
void disable_nmi_singlestep(struct vcpu_svm *svm);
|
||||
|
||||
/* nested.c */
|
||||
|
||||
#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
|
||||
#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
|
||||
#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
|
||||
|
||||
/* This function returns true if it is save to enable the nmi window */
|
||||
static inline bool nested_svm_nmi(struct vcpu_svm *svm)
|
||||
{
|
||||
if (!is_guest_mode(&svm->vcpu))
|
||||
return true;
|
||||
|
||||
if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
|
||||
return true;
|
||||
|
||||
svm->vmcb->control.exit_code = SVM_EXIT_NMI;
|
||||
svm->nested.exit_required = true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
|
||||
}
|
||||
|
||||
void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
|
||||
struct vmcb *nested_vmcb, struct kvm_host_map *map);
|
||||
int nested_svm_vmrun(struct vcpu_svm *svm);
|
||||
void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
|
||||
int nested_svm_vmexit(struct vcpu_svm *svm);
|
||||
int nested_svm_exit_handled(struct vcpu_svm *svm);
|
||||
int nested_svm_check_permissions(struct vcpu_svm *svm);
|
||||
int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
|
||||
bool has_error_code, u32 error_code);
|
||||
int svm_check_nested_events(struct kvm_vcpu *vcpu);
|
||||
int nested_svm_exit_special(struct vcpu_svm *svm);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue