mirror of https://gitee.com/openkylin/linux.git
b43: N-PHY: reorder functions: collect radio ones
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Rafał Miłecki
John W. Linville
parent
ab499217dc
commit
884a5228a2
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@ -414,60 +414,9 @@ static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
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}
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/**************************************************
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* Others
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* Radio 0x2056
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**************************************************/
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void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
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{//TODO
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}
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static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
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{//TODO
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}
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static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
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bool ignore_tssi)
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{//TODO
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return B43_TXPWR_RES_DONE;
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}
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static void b43_chantab_radio_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry_rev2 *e)
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{
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b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
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b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
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b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
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b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
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b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
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b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
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b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
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b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
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b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
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b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
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b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
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b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
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b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
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b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
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b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
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b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
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b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
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}
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static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry_rev3 *e)
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{
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@ -649,6 +598,203 @@ static void b43_radio_2056_setup(struct b43_wldev *dev,
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udelay(300);
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}
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static void b43_radio_init2056_pre(struct b43_wldev *dev)
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{
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b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
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~B43_NPHY_RFCTL_CMD_CHIP0PU);
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/* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
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b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_OEPORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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~B43_NPHY_RFCTL_CMD_OEPORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_CHIP0PU);
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}
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static void b43_radio_init2056_post(struct b43_wldev *dev)
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{
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b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
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b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
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b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
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msleep(1);
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b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
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b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
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b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
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/*
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if (nphy->init_por)
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Call Radio 2056 Recalibrate
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*/
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}
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/*
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* Initialize a Broadcom 2056 N-radio
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* http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
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*/
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static void b43_radio_init2056(struct b43_wldev *dev)
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{
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b43_radio_init2056_pre(dev);
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b2056_upload_inittabs(dev, 0, 0);
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b43_radio_init2056_post(dev);
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}
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/**************************************************
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* Radio 0x2055
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**************************************************/
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static void b43_chantab_radio_upload(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry_rev2 *e)
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{
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b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
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b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
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b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
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b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
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b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
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b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
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b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
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b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
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b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
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b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
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b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
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b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
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b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
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b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
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b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
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b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
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b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
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static void b43_radio_2055_setup(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry_rev2 *e)
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{
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B43_WARN_ON(dev->phy.rev >= 3);
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b43_chantab_radio_upload(dev, e);
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udelay(50);
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b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
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b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
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udelay(300);
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}
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static void b43_radio_init2055_pre(struct b43_wldev *dev)
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{
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b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
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~B43_NPHY_RFCTL_CMD_PORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_CHIP0PU |
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B43_NPHY_RFCTL_CMD_OEPORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_PORFORCE);
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}
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static void b43_radio_init2055_post(struct b43_wldev *dev)
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{
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struct b43_phy_n *nphy = dev->phy.n;
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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int i;
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u16 val;
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bool workaround = false;
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if (sprom->revision < 4)
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workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
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&& dev->dev->board_type == 0x46D
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&& dev->dev->board_rev >= 0x41);
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else
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workaround =
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!(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
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b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
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if (workaround) {
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b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
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b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
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}
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b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
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b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
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b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
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b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
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b43_radio_set(dev, B2055_CAL_MISC, 0x1);
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msleep(1);
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b43_radio_set(dev, B2055_CAL_MISC, 0x40);
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for (i = 0; i < 200; i++) {
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val = b43_radio_read(dev, B2055_CAL_COUT2);
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if (val & 0x80) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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b43err(dev->wl, "radio post init timeout\n");
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b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
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b43_switch_channel(dev, dev->phy.channel);
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b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
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b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
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b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
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b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
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b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
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b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
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if (!nphy->gain_boost) {
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b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
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b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
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} else {
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b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
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b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
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}
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udelay(2);
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}
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/*
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* Initialize a Broadcom 2055 N-radio
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* http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
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*/
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static void b43_radio_init2055(struct b43_wldev *dev)
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{
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b43_radio_init2055_pre(dev);
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if (b43_status(dev) < B43_STAT_INITIALIZED) {
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/* Follow wl, not specs. Do not force uploading all regs */
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b2055_upload_inittab(dev, 0, 0);
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} else {
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bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
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b2055_upload_inittab(dev, ghz5, 0);
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}
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b43_radio_init2055_post(dev);
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}
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/**************************************************
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* Others
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**************************************************/
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void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
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{//TODO
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}
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static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
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{//TODO
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}
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static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
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bool ignore_tssi)
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{//TODO
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return B43_TXPWR_RES_DONE;
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}
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static void b43_chantab_phy_upload(struct b43_wldev *dev,
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const struct b43_phy_n_sfo_cfg *e)
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{
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@ -952,144 +1098,6 @@ static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
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}
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
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static void b43_radio_2055_setup(struct b43_wldev *dev,
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const struct b43_nphy_channeltab_entry_rev2 *e)
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{
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B43_WARN_ON(dev->phy.rev >= 3);
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b43_chantab_radio_upload(dev, e);
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udelay(50);
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b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
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b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
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b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
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b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
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udelay(300);
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}
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static void b43_radio_init2055_pre(struct b43_wldev *dev)
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{
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b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
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~B43_NPHY_RFCTL_CMD_PORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_CHIP0PU |
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B43_NPHY_RFCTL_CMD_OEPORFORCE);
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b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
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B43_NPHY_RFCTL_CMD_PORFORCE);
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}
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static void b43_radio_init2055_post(struct b43_wldev *dev)
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{
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struct b43_phy_n *nphy = dev->phy.n;
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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int i;
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u16 val;
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bool workaround = false;
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if (sprom->revision < 4)
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workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
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&& dev->dev->board_type == 0x46D
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&& dev->dev->board_rev >= 0x41);
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else
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workaround =
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!(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
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b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
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if (workaround) {
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b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
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b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
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}
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b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
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b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
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b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
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b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
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b43_radio_set(dev, B2055_CAL_MISC, 0x1);
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msleep(1);
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b43_radio_set(dev, B2055_CAL_MISC, 0x40);
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for (i = 0; i < 200; i++) {
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val = b43_radio_read(dev, B2055_CAL_COUT2);
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if (val & 0x80) {
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i = 0;
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break;
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}
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udelay(10);
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}
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if (i)
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b43err(dev->wl, "radio post init timeout\n");
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b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
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b43_switch_channel(dev, dev->phy.channel);
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b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
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b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
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b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
|
||||
b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
|
||||
b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
|
||||
b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
|
||||
if (!nphy->gain_boost) {
|
||||
b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
|
||||
b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
|
||||
} else {
|
||||
b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
|
||||
b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
|
||||
}
|
||||
udelay(2);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize a Broadcom 2055 N-radio
|
||||
* http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
|
||||
*/
|
||||
static void b43_radio_init2055(struct b43_wldev *dev)
|
||||
{
|
||||
b43_radio_init2055_pre(dev);
|
||||
if (b43_status(dev) < B43_STAT_INITIALIZED) {
|
||||
/* Follow wl, not specs. Do not force uploading all regs */
|
||||
b2055_upload_inittab(dev, 0, 0);
|
||||
} else {
|
||||
bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
|
||||
b2055_upload_inittab(dev, ghz5, 0);
|
||||
}
|
||||
b43_radio_init2055_post(dev);
|
||||
}
|
||||
|
||||
static void b43_radio_init2056_pre(struct b43_wldev *dev)
|
||||
{
|
||||
b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
||||
~B43_NPHY_RFCTL_CMD_CHIP0PU);
|
||||
/* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
|
||||
b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
|
||||
B43_NPHY_RFCTL_CMD_OEPORFORCE);
|
||||
b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
||||
~B43_NPHY_RFCTL_CMD_OEPORFORCE);
|
||||
b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
|
||||
B43_NPHY_RFCTL_CMD_CHIP0PU);
|
||||
}
|
||||
|
||||
static void b43_radio_init2056_post(struct b43_wldev *dev)
|
||||
{
|
||||
b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
|
||||
b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
|
||||
b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
|
||||
msleep(1);
|
||||
b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
|
||||
b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
|
||||
b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
|
||||
/*
|
||||
if (nphy->init_por)
|
||||
Call Radio 2056 Recalibrate
|
||||
*/
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize a Broadcom 2056 N-radio
|
||||
* http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
|
||||
*/
|
||||
static void b43_radio_init2056(struct b43_wldev *dev)
|
||||
{
|
||||
b43_radio_init2056_pre(dev);
|
||||
b2056_upload_inittabs(dev, 0, 0);
|
||||
b43_radio_init2056_post(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Upload the N-PHY tables.
|
||||
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
|
||||
|
|
|
|||
Loading…
Reference in New Issue