mirror of https://gitee.com/openkylin/linux.git
ath5k: Update RF Buffer handling
* Use the new way to modify rf buffer and put some rf buffer documentation on rfbufer.h * Merge all rf regs functions to one * Sync with legacy HAL and Sam's HAL * Set gain_F settings so that gain_F optimization engine works on RF5111/RF5112 (note that both HALs only use step 0 for RF5111 and they don't use gain_F optimization for this chip, code is there but is never used) Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
John W. Linville
parent
6f3b414aca
commit
8892e4ec62
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@ -165,9 +165,6 @@
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#define AR5K_INI_VAL_XR 0
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#define AR5K_INI_VAL_MAX 5
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#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
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#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
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/* Used for BSSID etc manipulation */
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#define AR5K_LOW_ID(_a)( \
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(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
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@ -342,6 +339,7 @@ struct ath5k_srev_name {
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#define AR5K_SREV_PHY_5211 0x30
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#define AR5K_SREV_PHY_5212 0x41
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#define AR5K_SREV_PHY_5212A 0x42
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#define AR5K_SREV_PHY_2112B 0x43
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#define AR5K_SREV_PHY_2413 0x45
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#define AR5K_SREV_PHY_5413 0x61
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@ -1083,8 +1081,9 @@ struct ath5k_hw {
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u32 ah_txq_isr;
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u32 *ah_rf_banks;
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size_t ah_rf_banks_size;
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size_t ah_rf_regs_count;
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struct ath5k_gain ah_gain;
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u32 ah_offset[AR5K_MAX_RF_BANKS];
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u8 ah_offset[AR5K_MAX_RF_BANKS];
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struct {
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u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
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@ -1232,7 +1231,9 @@ extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
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extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
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/* Initialize RF */
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extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
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extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
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struct ieee80211_channel *channel,
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unsigned int mode);
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extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
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extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
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extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
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@ -32,48 +32,80 @@
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/*
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* Used to modify RF Banks before writing them to AR5K_RF_BUFFER
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*/
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static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
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u32 first, u32 col, bool set)
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static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
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const struct ath5k_rf_reg *rf_regs,
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u32 val, u8 reg_id, bool set)
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{
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u32 mask, entry, last, data, shift, position;
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s32 left;
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const struct ath5k_rf_reg *rfreg = NULL;
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u8 offset, bank, num_bits, col, position;
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u16 entry;
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u32 mask, data, last_bit, bits_shifted, first_bit;
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u32 *rfb;
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s32 bits_left;
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int i;
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data = 0;
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rfb = ah->ah_rf_banks;
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if (rf == NULL)
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for (i = 0; i < ah->ah_rf_regs_count; i++) {
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if (rf_regs[i].index == reg_id) {
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rfreg = &rf_regs[i];
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break;
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}
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}
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if (rfb == NULL || rfreg == NULL) {
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ATH5K_PRINTF("Rf register not found!\n");
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/* should not happen */
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return 0;
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}
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if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
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bank = rfreg->bank;
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num_bits = rfreg->field.len;
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first_bit = rfreg->field.pos;
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col = rfreg->field.col;
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/* first_bit is an offset from bank's
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* start. Since we have all banks on
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* the same array, we use this offset
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* to mark each bank's start */
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offset = ah->ah_offset[bank];
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/* Boundary check */
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if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
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ATH5K_PRINTF("invalid values at offset %u\n", offset);
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return 0;
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}
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entry = ((first - 1) / 8) + offset;
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position = (first - 1) % 8;
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entry = ((first_bit - 1) / 8) + offset;
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position = (first_bit - 1) % 8;
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if (set)
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data = ath5k_hw_bitswap(reg, bits);
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data = ath5k_hw_bitswap(val, num_bits);
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for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
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last = (position + left > 8) ? 8 : position + left;
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mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
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for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
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position = 0, entry++) {
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last_bit = (position + bits_left > 8) ? 8 :
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position + bits_left;
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mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
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(col * 8);
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if (set) {
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rf[entry] &= ~mask;
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rf[entry] |= ((data << position) << (col * 8)) & mask;
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rfb[entry] &= ~mask;
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rfb[entry] |= ((data << position) << (col * 8)) & mask;
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data >>= (8 - position);
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} else {
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data = (((rf[entry] & mask) >> (col * 8)) >> position)
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<< shift;
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shift += last - position;
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data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
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<< bits_shifted;
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bits_shifted += last_bit - position;
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}
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left -= 8 - position;
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bits_left -= 8 - position;
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}
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data = set ? 1 : ath5k_hw_bitswap(data, bits);
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data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
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return data;
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}
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@ -167,6 +199,7 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
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u32 *rf;
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const struct ath5k_gain_opt *go;
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const struct ath5k_gain_opt_step *g_step;
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const struct ath5k_rf_reg *rf_regs;
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/* Only RF5112 Rev. 2 supports it */
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if ((ah->ah_radio != AR5K_RF5112) ||
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@ -174,6 +207,8 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
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return 0;
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go = &rfgain_opt_5112;
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rf_regs = rf_regs_5112a;
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ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
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g_step = &go->go_step[ah->ah_gain.g_step_idx];
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@ -184,11 +219,11 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
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ah->ah_gain.g_f_corr = 0;
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/* No VGA (Variable Gain Amplifier) override, skip */
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if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
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if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
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return 0;
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/* Mix gain stepping */
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step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
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step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
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/* Mix gain override */
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mix = g_step->gos_param[0];
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@ -217,6 +252,7 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
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* their detection window) so we must ignore it */
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static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
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{
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const struct ath5k_rf_reg *rf_regs;
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u32 step, mix_ovr, level[4];
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u32 *rf;
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@ -226,8 +262,13 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
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rf = ah->ah_rf_banks;
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if (ah->ah_radio == AR5K_RF5111) {
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step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
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false);
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rf_regs = rf_regs_5111;
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ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
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step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
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false);
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level[0] = 0;
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level[1] = (step == 63) ? 50 : step + 4;
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level[2] = (step != 63) ? 64 : level[0];
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@ -238,8 +279,13 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
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ah->ah_gain.g_low = level[0] +
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(step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
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} else {
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mix_ovr = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
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false);
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rf_regs = rf_regs_5112;
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ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
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mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
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false);
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level[0] = level[2] = 0;
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if (mix_ovr == 1) {
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@ -451,341 +497,320 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
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* RF Registers setup *
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\********************/
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/*
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* Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
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*/
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static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
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struct ieee80211_channel *channel, unsigned int mode)
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{
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struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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u32 *rf;
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const unsigned int rf_size = ARRAY_SIZE(rfb_5111);
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unsigned int i;
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int obdb = -1, bank = -1;
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u32 ee_mode;
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AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
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rf = ah->ah_rf_banks;
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/* Copy values to modify them */
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for (i = 0; i < rf_size; i++) {
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if (rfb_5111[i].rfb_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
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ATH5K_ERR(ah->ah_sc, "invalid bank\n");
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return -EINVAL;
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}
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if (bank != rfb_5111[i].rfb_bank) {
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bank = rfb_5111[i].rfb_bank;
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ah->ah_offset[bank] = i;
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}
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rf[i] = rfb_5111[i].rfb_mode_data[mode];
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}
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/* Modify bank 0 */
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if (channel->hw_value & CHANNEL_2GHZ) {
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if (channel->hw_value & CHANNEL_CCK)
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ee_mode = AR5K_EEPROM_MODE_11B;
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else
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ee_mode = AR5K_EEPROM_MODE_11G;
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obdb = 0;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
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ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
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ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
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return -EINVAL;
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obdb = 1;
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/* Modify bank 6 */
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} else {
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/* For 11a, Turbo and XR */
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ee_mode = AR5K_EEPROM_MODE_11A;
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obdb = channel->center_freq >= 5725 ? 3 :
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(channel->center_freq >= 5500 ? 2 :
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(channel->center_freq >= 5260 ? 1 :
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(channel->center_freq > 4000 ? 0 : -1)));
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_pwd_84, 1, 51, 3, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_pwd_90, 1, 45, 3, true))
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return -EINVAL;
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}
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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!ee->ee_xpd[ee_mode], 1, 95, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_x_gain[ee_mode], 4, 96, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
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ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
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ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
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return -EINVAL;
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/* Modify bank 7 */
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
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ee->ee_i_gain[ee_mode], 6, 29, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
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ee->ee_xpd[ee_mode], 1, 4, 0, true))
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return -EINVAL;
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/* Write RF values */
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for (i = 0; i < rf_size; i++) {
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AR5K_REG_WAIT(i);
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ath5k_hw_reg_write(ah, rf[i], rfb_5111[i].rfb_ctrl_register);
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}
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ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
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return 0;
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}
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/*
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* Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
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* Setup RF registers by writing rf buffer on hw
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*/
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static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
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struct ieee80211_channel *channel, unsigned int mode)
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{
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const struct ath5k_ini_rfbuffer *rf_ini;
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struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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u32 *rf;
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unsigned int rf_size, i;
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int obdb = -1, bank = -1;
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u32 ee_mode;
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AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
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rf = ah->ah_rf_banks;
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if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
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rf_ini = rfb_5112a;
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rf_size = ARRAY_SIZE(rfb_5112a);
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} else {
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rf_ini = rfb_5112;
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rf_size = ARRAY_SIZE(rfb_5112);
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}
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/* Copy values to modify them */
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for (i = 0; i < rf_size; i++) {
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if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
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ATH5K_ERR(ah->ah_sc, "invalid bank\n");
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return -EINVAL;
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}
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if (bank != rf_ini[i].rfb_bank) {
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bank = rf_ini[i].rfb_bank;
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ah->ah_offset[bank] = i;
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}
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rf[i] = rf_ini[i].rfb_mode_data[mode];
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}
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/* Modify bank 6 */
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if (channel->hw_value & CHANNEL_2GHZ) {
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if (channel->hw_value & CHANNEL_OFDM)
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ee_mode = AR5K_EEPROM_MODE_11G;
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else
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ee_mode = AR5K_EEPROM_MODE_11B;
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obdb = 0;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
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return -EINVAL;
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} else {
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/* For 11a, Turbo and XR */
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ee_mode = AR5K_EEPROM_MODE_11A;
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obdb = channel->center_freq >= 5725 ? 3 :
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(channel->center_freq >= 5500 ? 2 :
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(channel->center_freq >= 5260 ? 1 :
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(channel->center_freq > 4000 ? 0 : -1)));
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if (obdb == -1)
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
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return -EINVAL;
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if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
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return -EINVAL;
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}
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ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
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ee->ee_x_gain[ee_mode], 2, 270, 0, true);
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ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
|
||||
ee->ee_x_gain[ee_mode], 2, 257, 0, true);
|
||||
|
||||
if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
|
||||
ee->ee_xpd[ee_mode], 1, 302, 0, true))
|
||||
return -EINVAL;
|
||||
|
||||
/* Modify bank 7 */
|
||||
if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
|
||||
ee->ee_i_gain[ee_mode], 6, 14, 0, true))
|
||||
return -EINVAL;
|
||||
|
||||
/* Write RF values */
|
||||
for (i = 0; i < rf_size; i++)
|
||||
ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
|
||||
|
||||
|
||||
ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize RF5413/5414 and future chips
|
||||
* (until we come up with a better solution)
|
||||
*/
|
||||
static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
|
||||
struct ieee80211_channel *channel, unsigned int mode)
|
||||
{
|
||||
const struct ath5k_ini_rfbuffer *rf_ini;
|
||||
u32 *rf;
|
||||
unsigned int rf_size, i;
|
||||
int bank = -1;
|
||||
|
||||
AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
|
||||
|
||||
rf = ah->ah_rf_banks;
|
||||
|
||||
switch (ah->ah_radio) {
|
||||
case AR5K_RF5413:
|
||||
rf_ini = rfb_5413;
|
||||
rf_size = ARRAY_SIZE(rfb_5413);
|
||||
break;
|
||||
case AR5K_RF2413:
|
||||
rf_ini = rfb_2413;
|
||||
rf_size = ARRAY_SIZE(rfb_2413);
|
||||
|
||||
if (mode < 2) {
|
||||
ATH5K_ERR(ah->ah_sc,
|
||||
"invalid channel mode: %i\n", mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
break;
|
||||
case AR5K_RF2425:
|
||||
rf_ini = rfb_2425;
|
||||
rf_size = ARRAY_SIZE(rfb_2425);
|
||||
|
||||
if (mode < 2) {
|
||||
ATH5K_ERR(ah->ah_sc,
|
||||
"invalid channel mode: %i\n", mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Copy values to modify them */
|
||||
for (i = 0; i < rf_size; i++) {
|
||||
if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
|
||||
ATH5K_ERR(ah->ah_sc, "invalid bank\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (bank != rf_ini[i].rfb_bank) {
|
||||
bank = rf_ini[i].rfb_bank;
|
||||
ah->ah_offset[bank] = i;
|
||||
}
|
||||
|
||||
rf[i] = rf_ini[i].rfb_mode_data[mode];
|
||||
}
|
||||
|
||||
/*
|
||||
* After compairing dumps from different cards
|
||||
* we get the same RF_BUFFER settings (diff returns
|
||||
* 0 lines). It seems that RF_BUFFER settings are static
|
||||
* and are written unmodified (no EEPROM stuff
|
||||
* is used because calibration data would be
|
||||
* different between different cards and would result
|
||||
* different RF_BUFFER settings)
|
||||
*/
|
||||
|
||||
/* Write RF values */
|
||||
for (i = 0; i < rf_size; i++)
|
||||
ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize RF
|
||||
*/
|
||||
int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
|
||||
int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
|
||||
unsigned int mode)
|
||||
{
|
||||
int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
|
||||
int ret;
|
||||
const struct ath5k_rf_reg *rf_regs;
|
||||
const struct ath5k_ini_rfbuffer *ini_rfb;
|
||||
const struct ath5k_gain_opt *go = NULL;
|
||||
const struct ath5k_gain_opt_step *g_step;
|
||||
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
|
||||
u8 ee_mode = 0;
|
||||
u32 *rfb;
|
||||
int i, obdb = -1, bank = -1;
|
||||
|
||||
switch (ah->ah_radio) {
|
||||
case AR5K_RF5111:
|
||||
ah->ah_rf_banks_size = sizeof(rfb_5111);
|
||||
func = ath5k_hw_rf5111_rfregs;
|
||||
rf_regs = rf_regs_5111;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
|
||||
ini_rfb = rfb_5111;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
|
||||
go = &rfgain_opt_5111;
|
||||
break;
|
||||
case AR5K_RF5112:
|
||||
if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
|
||||
ah->ah_rf_banks_size = sizeof(rfb_5112a);
|
||||
else
|
||||
ah->ah_rf_banks_size = sizeof(rfb_5112);
|
||||
func = ath5k_hw_rf5112_rfregs;
|
||||
break;
|
||||
case AR5K_RF5413:
|
||||
ah->ah_rf_banks_size = sizeof(rfb_5413);
|
||||
func = ath5k_hw_rf5413_rfregs;
|
||||
if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
|
||||
rf_regs = rf_regs_5112a;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
|
||||
ini_rfb = rfb_5112a;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
|
||||
} else {
|
||||
rf_regs = rf_regs_5112;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
|
||||
ini_rfb = rfb_5112;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
|
||||
}
|
||||
go = &rfgain_opt_5112;
|
||||
break;
|
||||
case AR5K_RF2413:
|
||||
ah->ah_rf_banks_size = sizeof(rfb_2413);
|
||||
func = ath5k_hw_rf5413_rfregs;
|
||||
rf_regs = rf_regs_2413;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
|
||||
ini_rfb = rfb_2413;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
|
||||
break;
|
||||
case AR5K_RF2316:
|
||||
rf_regs = rf_regs_2316;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
|
||||
ini_rfb = rfb_2316;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
|
||||
break;
|
||||
case AR5K_RF5413:
|
||||
rf_regs = rf_regs_5413;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
|
||||
ini_rfb = rfb_5413;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
|
||||
break;
|
||||
case AR5K_RF2317:
|
||||
rf_regs = rf_regs_2425;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
|
||||
ini_rfb = rfb_2317;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
|
||||
break;
|
||||
case AR5K_RF2425:
|
||||
ah->ah_rf_banks_size = sizeof(rfb_2425);
|
||||
func = ath5k_hw_rf5413_rfregs;
|
||||
rf_regs = rf_regs_2425;
|
||||
ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
|
||||
if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
|
||||
ini_rfb = rfb_2425;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
|
||||
} else {
|
||||
ini_rfb = rfb_2417;
|
||||
ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* If it's the first time we set rf buffer, allocate
|
||||
* ah->ah_rf_banks based on ah->ah_rf_banks_size
|
||||
* we set above */
|
||||
if (ah->ah_rf_banks == NULL) {
|
||||
/* XXX do extra checks? */
|
||||
ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
|
||||
ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
|
||||
GFP_KERNEL);
|
||||
if (ah->ah_rf_banks == NULL) {
|
||||
ATH5K_ERR(ah->ah_sc, "out of memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
|
||||
ret = func(ah, channel, mode);
|
||||
/* Copy values to modify them */
|
||||
rfb = ah->ah_rf_banks;
|
||||
|
||||
return ret;
|
||||
for (i = 0; i < ah->ah_rf_banks_size; i++) {
|
||||
if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
|
||||
ATH5K_ERR(ah->ah_sc, "invalid bank\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Bank changed, write down the offset */
|
||||
if (bank != ini_rfb[i].rfb_bank) {
|
||||
bank = ini_rfb[i].rfb_bank;
|
||||
ah->ah_offset[bank] = i;
|
||||
}
|
||||
|
||||
rfb[i] = ini_rfb[i].rfb_mode_data[mode];
|
||||
}
|
||||
|
||||
/* Set Output and Driver bias current (OB/DB) */
|
||||
if (channel->hw_value & CHANNEL_2GHZ) {
|
||||
|
||||
if (channel->hw_value & CHANNEL_CCK)
|
||||
ee_mode = AR5K_EEPROM_MODE_11B;
|
||||
else
|
||||
ee_mode = AR5K_EEPROM_MODE_11G;
|
||||
|
||||
/* For RF511X/RF211X combination we
|
||||
* use b_OB and b_DB parameters stored
|
||||
* in eeprom on ee->ee_ob[ee_mode][0]
|
||||
*
|
||||
* For all other chips we use OB/DB for 2Ghz
|
||||
* stored in the b/g modal section just like
|
||||
* 802.11a on ee->ee_ob[ee_mode][1] */
|
||||
if ((ah->ah_radio == AR5K_RF5111) ||
|
||||
(ah->ah_radio == AR5K_RF5112))
|
||||
obdb = 0;
|
||||
else
|
||||
obdb = 1;
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
|
||||
AR5K_RF_OB_2GHZ, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
|
||||
AR5K_RF_DB_2GHZ, true);
|
||||
|
||||
/* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
|
||||
} else if ((channel->hw_value & CHANNEL_5GHZ) ||
|
||||
(ah->ah_radio == AR5K_RF5111)) {
|
||||
|
||||
/* For 11a, Turbo and XR we need to choose
|
||||
* OB/DB based on frequency range */
|
||||
ee_mode = AR5K_EEPROM_MODE_11A;
|
||||
obdb = channel->center_freq >= 5725 ? 3 :
|
||||
(channel->center_freq >= 5500 ? 2 :
|
||||
(channel->center_freq >= 5260 ? 1 :
|
||||
(channel->center_freq > 4000 ? 0 : -1)));
|
||||
|
||||
if (obdb < 0)
|
||||
return -EINVAL;
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
|
||||
AR5K_RF_OB_5GHZ, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
|
||||
AR5K_RF_DB_5GHZ, true);
|
||||
}
|
||||
|
||||
g_step = &go->go_step[ah->ah_gain.g_step_idx];
|
||||
|
||||
/* Bank Modifications (chip-specific) */
|
||||
if (ah->ah_radio == AR5K_RF5111) {
|
||||
|
||||
/* Set gain_F settings according to current step */
|
||||
if (channel->hw_value & CHANNEL_OFDM) {
|
||||
|
||||
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
|
||||
AR5K_PHY_FRAME_CTL_TX_CLIP,
|
||||
g_step->gos_param[0]);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
|
||||
AR5K_RF_PWD_90, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
|
||||
AR5K_RF_PWD_84, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
|
||||
AR5K_RF_RFGAIN_SEL, true);
|
||||
|
||||
/* We programmed gain_F parameters, switch back
|
||||
* to active state */
|
||||
ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
|
||||
|
||||
}
|
||||
|
||||
/* Bank 6/7 setup */
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
|
||||
AR5K_RF_PWD_XPD, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
|
||||
AR5K_RF_XPD_GAIN, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
|
||||
AR5K_RF_GAIN_I, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
|
||||
AR5K_RF_PLO_SEL, true);
|
||||
|
||||
/* TODO: Half/quarter channel support */
|
||||
}
|
||||
|
||||
if (ah->ah_radio == AR5K_RF5112) {
|
||||
|
||||
/* Set gain_F settings according to current step */
|
||||
if (channel->hw_value & CHANNEL_OFDM) {
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
|
||||
AR5K_RF_MIXGAIN_OVR, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
|
||||
AR5K_RF_PWD_138, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
|
||||
AR5K_RF_PWD_137, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
|
||||
AR5K_RF_PWD_136, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
|
||||
AR5K_RF_PWD_132, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
|
||||
AR5K_RF_PWD_131, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
|
||||
AR5K_RF_PWD_130, true);
|
||||
|
||||
/* We programmed gain_F parameters, switch back
|
||||
* to active state */
|
||||
ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
|
||||
}
|
||||
|
||||
/* Bank 6/7 setup */
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
|
||||
AR5K_RF_XPD_SEL, true);
|
||||
|
||||
if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
|
||||
/* Rev. 1 supports only one xpd */
|
||||
ath5k_hw_rfb_op(ah, rf_regs,
|
||||
ee->ee_x_gain[ee_mode],
|
||||
AR5K_RF_XPD_GAIN, true);
|
||||
|
||||
} else {
|
||||
/* TODO: Set high and low gain bits */
|
||||
ath5k_hw_rfb_op(ah, rf_regs,
|
||||
ee->ee_x_gain[ee_mode],
|
||||
AR5K_RF_PD_GAIN_LO, true);
|
||||
ath5k_hw_rfb_op(ah, rf_regs,
|
||||
ee->ee_x_gain[ee_mode],
|
||||
AR5K_RF_PD_GAIN_HI, true);
|
||||
|
||||
/* Lower synth voltage on Rev 2 */
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 2,
|
||||
AR5K_RF_HIGH_VC_CP, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 2,
|
||||
AR5K_RF_MID_VC_CP, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 2,
|
||||
AR5K_RF_LOW_VC_CP, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 2,
|
||||
AR5K_RF_PUSH_UP, true);
|
||||
|
||||
/* Decrease power consumption on 5213+ BaseBand */
|
||||
if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 1,
|
||||
AR5K_RF_PAD2GND, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 1,
|
||||
AR5K_RF_XB2_LVL, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 1,
|
||||
AR5K_RF_XB5_LVL, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 1,
|
||||
AR5K_RF_PWD_167, true);
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 1,
|
||||
AR5K_RF_PWD_166, true);
|
||||
}
|
||||
}
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
|
||||
AR5K_RF_GAIN_I, true);
|
||||
|
||||
/* TODO: Half/quarter channel support */
|
||||
|
||||
}
|
||||
|
||||
if (ah->ah_radio == AR5K_RF5413 &&
|
||||
channel->hw_value & CHANNEL_2GHZ) {
|
||||
|
||||
ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
|
||||
true);
|
||||
|
||||
/* Set optimum value for early revisions (on pci-e chips) */
|
||||
if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
|
||||
ah->ah_mac_srev < AR5K_SREV_AR5413)
|
||||
ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
|
||||
AR5K_RF_PWD_ICLOBUF_2G, true);
|
||||
|
||||
}
|
||||
|
||||
/* Write RF banks on hw */
|
||||
for (i = 0; i < ah->ah_rf_banks_size; i++) {
|
||||
AR5K_REG_WAIT(i);
|
||||
ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**************************\
|
||||
PHY/RF channel functions
|
||||
\**************************/
|
||||
|
|
|
|||
|
|
@ -2101,34 +2101,10 @@
|
|||
/*
|
||||
* RF Buffer register
|
||||
*
|
||||
* There are some special control registers on the RF chip
|
||||
* that hold various operation settings related mostly to
|
||||
* the analog parts (channel, gain adjustment etc).
|
||||
*
|
||||
* We don't write on those registers directly but
|
||||
* we send a data packet on the buffer register and
|
||||
* then write on another special register to notify hw
|
||||
* to apply the settings. This is done so that control registers
|
||||
* can be dynamicaly programmed during operation and the settings
|
||||
* are applied faster on the hw.
|
||||
*
|
||||
* We sent such data packets during rf initialization and channel change
|
||||
* through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions.
|
||||
*
|
||||
* The data packets we send during initializadion are inside ath5k_ini_rf
|
||||
* struct (see ath5k_hw.h) and each one is related to an "rf register bank".
|
||||
* We use *rfregs functions to modify them acording to current operation
|
||||
* mode and eeprom values and pass them all together to the chip.
|
||||
*
|
||||
* It's obvious from the code that 0x989c is the buffer register but
|
||||
* for the other special registers that we write to after sending each
|
||||
* packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers
|
||||
* for now. It's interesting that they are also used for some other operations.
|
||||
*
|
||||
* Also check out hw.h and U.S. Patent 6677779 B1 (about buffer
|
||||
* registers and control registers):
|
||||
*
|
||||
* http://www.google.com/patents?id=qNURAAAAEBAJ
|
||||
*/
|
||||
|
||||
#define AR5K_RF_BUFFER 0x989c
|
||||
|
|
|
|||
|
|
@ -600,7 +600,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
|||
/*
|
||||
* Write RF registers
|
||||
*/
|
||||
ret = ath5k_hw_rfregs(ah, channel, mode);
|
||||
ret = ath5k_hw_rfregs_init(ah, channel, mode);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,33 @@
|
|||
*
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* There are some special registers on the RF chip
|
||||
* that control various operation settings related mostly to
|
||||
* the analog parts (channel, gain adjustment etc).
|
||||
*
|
||||
* We don't write on those registers directly but
|
||||
* we send a data packet on the chip, using a special register,
|
||||
* that holds all the settings we need. After we 've sent the
|
||||
* data packet, we write on another special register to notify hw
|
||||
* to apply the settings. This is done so that control registers
|
||||
* can be dynamicaly programmed during operation and the settings
|
||||
* are applied faster on the hw.
|
||||
*
|
||||
* We call each data packet an "RF Bank" and all the data we write
|
||||
* (all RF Banks) "RF Buffer". This file holds initial RF Buffer
|
||||
* data for the different RF chips, and various info to match RF
|
||||
* Buffer offsets with specific RF registers so that we can access
|
||||
* them. We tweak these settings on rfregs_init function.
|
||||
*
|
||||
* Also check out reg.h and U.S. Patent 6677779 B1 (about buffer
|
||||
* registers and control registers):
|
||||
*
|
||||
* http://www.google.com/patents?id=qNURAAAAEBAJ
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Struct to hold default mode specific RF
|
||||
* register values (RF Banks)
|
||||
|
|
@ -72,15 +99,28 @@ enum ath5k_rf_regs_idx {
|
|||
AR5K_RF_XB2_LVL,
|
||||
AR5K_RF_XB5_LVL,
|
||||
AR5K_RF_PWD_ICLOBUF_2G,
|
||||
AR5K_RF_PWD_84,
|
||||
AR5K_RF_PWD_90,
|
||||
AR5K_RF_PWD_130,
|
||||
AR5K_RF_PWD_131,
|
||||
AR5K_RF_PWD_132,
|
||||
AR5K_RF_PWD_136,
|
||||
AR5K_RF_PWD_137,
|
||||
AR5K_RF_PWD_138,
|
||||
AR5K_RF_PWD_166,
|
||||
AR5K_RF_PWD_167,
|
||||
AR5K_RF_DERBY_CHAN_SEL_MODE,
|
||||
/* BANK 7 */
|
||||
AR5K_RF_GAIN_I,
|
||||
AR5K_RF_PLO_SEL,
|
||||
AR5K_RF_RFGAIN_SEL,
|
||||
AR5K_RF_RFGAIN_STEP,
|
||||
AR5K_RF_WAIT_S,
|
||||
AR5K_RF_WAIT_I,
|
||||
AR5K_RF_MAX_TIME,
|
||||
AR5K_RF_MIXVGA_OVR,
|
||||
AR5K_RF_MIXGAIN_OVR,
|
||||
AR5K_RF_MIXGAIN_STEP,
|
||||
AR5K_RF_PD_DELAY_A,
|
||||
AR5K_RF_PD_DELAY_B,
|
||||
AR5K_RF_PD_DELAY_XR,
|
||||
|
|
@ -118,19 +158,21 @@ enum ath5k_rf_regs_idx {
|
|||
#define AR5K_RF5111_MAX_TIME { 2, 49, 0 }
|
||||
|
||||
static const struct ath5k_rf_reg rf_regs_5111[] = {
|
||||
{6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
|
||||
{6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
|
||||
{6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
|
||||
{6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
|
||||
{6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
|
||||
{6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
|
||||
{7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
|
||||
{7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
|
||||
{7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
|
||||
{7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
|
||||
{7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
|
||||
{7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
|
||||
|
||||
{6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
|
||||
{6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
|
||||
{6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
|
||||
{6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
|
||||
{6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
|
||||
{6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
|
||||
{6, AR5K_RF_PWD_84, AR5K_RF5111_PWD(84)},
|
||||
{6, AR5K_RF_PWD_90, AR5K_RF5111_PWD(90)},
|
||||
{7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
|
||||
{7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
|
||||
{7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
|
||||
{7, AR5K_RF_RFGAIN_STEP, AR5K_RF5111_RFGAIN_STEP},
|
||||
{7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
|
||||
{7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
|
||||
{7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
|
||||
};
|
||||
|
||||
/* Default mode specific settings */
|
||||
|
|
@ -273,8 +315,16 @@ static const struct ath5k_rf_reg rf_regs_5112[] = {
|
|||
{6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112_FIXED_BIAS_B},
|
||||
{6, AR5K_RF_XPD_SEL, AR5K_RF5112_XPD_SEL},
|
||||
{6, AR5K_RF_XPD_GAIN, AR5K_RF5112_XPD_GAIN},
|
||||
{6, AR5K_RF_PWD_130, AR5K_RF5112_PWD(130)},
|
||||
{6, AR5K_RF_PWD_131, AR5K_RF5112_PWD(131)},
|
||||
{6, AR5K_RF_PWD_132, AR5K_RF5112_PWD(132)},
|
||||
{6, AR5K_RF_PWD_136, AR5K_RF5112_PWD(136)},
|
||||
{6, AR5K_RF_PWD_137, AR5K_RF5112_PWD(137)},
|
||||
{6, AR5K_RF_PWD_138, AR5K_RF5112_PWD(138)},
|
||||
{7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
|
||||
{7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
|
||||
{7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
|
||||
{7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
|
||||
{7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
|
||||
{7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
|
||||
{7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
|
||||
|
|
@ -419,7 +469,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112[] = {
|
|||
#define AR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 }
|
||||
#define AR5K_RF5112A_MID_VC_CP { 2, 92, 2 }
|
||||
#define AR5K_RF5112A_LOW_VC_CP { 2, 94, 2 }
|
||||
#define AR5K_RF5112A_PUSH_UP { 2, 94, 2 }
|
||||
#define AR5K_RF5112A_PUSH_UP { 1, 254, 2 }
|
||||
|
||||
/* Power consumption */
|
||||
#define AR5K_RF5112A_PAD2GND { 1, 281, 1 }
|
||||
|
|
@ -436,6 +486,14 @@ static const struct ath5k_rf_reg rf_regs_5112a[] = {
|
|||
{6, AR5K_RF_XPD_SEL, AR5K_RF5112A_XPD_SEL},
|
||||
{6, AR5K_RF_PD_GAIN_LO, AR5K_RF5112A_PDGAINLO},
|
||||
{6, AR5K_RF_PD_GAIN_HI, AR5K_RF5112A_PDGAINHI},
|
||||
{6, AR5K_RF_PWD_130, AR5K_RF5112A_PWD(130)},
|
||||
{6, AR5K_RF_PWD_131, AR5K_RF5112A_PWD(131)},
|
||||
{6, AR5K_RF_PWD_132, AR5K_RF5112A_PWD(132)},
|
||||
{6, AR5K_RF_PWD_136, AR5K_RF5112A_PWD(136)},
|
||||
{6, AR5K_RF_PWD_137, AR5K_RF5112A_PWD(137)},
|
||||
{6, AR5K_RF_PWD_138, AR5K_RF5112A_PWD(138)},
|
||||
{6, AR5K_RF_PWD_166, AR5K_RF5112A_PWD(166)},
|
||||
{6, AR5K_RF_PWD_167, AR5K_RF5112A_PWD(167)},
|
||||
{6, AR5K_RF_HIGH_VC_CP, AR5K_RF5112A_HIGH_VC_CP},
|
||||
{6, AR5K_RF_MID_VC_CP, AR5K_RF5112A_MID_VC_CP},
|
||||
{6, AR5K_RF_LOW_VC_CP, AR5K_RF5112A_LOW_VC_CP},
|
||||
|
|
@ -444,7 +502,9 @@ static const struct ath5k_rf_reg rf_regs_5112a[] = {
|
|||
{6, AR5K_RF_XB2_LVL, AR5K_RF5112A_XB2_LVL},
|
||||
{6, AR5K_RF_XB5_LVL, AR5K_RF5112A_XB5_LVL},
|
||||
{7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
|
||||
{7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
|
||||
{7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
|
||||
{7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
|
||||
{7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
|
||||
{7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
|
||||
{7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
|
||||
|
|
|
|||
Loading…
Reference in New Issue