mirror of https://gitee.com/openkylin/linux.git
stmmac: intel: Add ADL-S 1Gbps PCI IDs
Added PCI IDs for both Ethernet TSN Controllers on the ADL-S. Also, skip SerDes programming sequences as these are being carried out at the BIOS level for ADL-S. Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com> Link: https://lore.kernel.org/r/20210126085832.3814-1-vee.khee.wong@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -457,6 +457,21 @@ static struct stmmac_pci_info tgl_sgmii1g_info = {
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.setup = tgl_sgmii_data,
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.setup = tgl_sgmii_data,
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};
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};
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static int adls_sgmii_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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plat->bus_id = 1;
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plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
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/* SerDes power up and power down are done in BIOS for ADL */
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return tgl_common_data(pdev, plat);
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}
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static struct stmmac_pci_info adls_sgmii1g_info = {
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.setup = adls_sgmii_data,
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};
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static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
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static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
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{
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{
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.func = 6,
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.func = 6,
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@ -724,6 +739,8 @@ static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
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#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac
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#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID 0x43ac
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#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2
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#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID 0x43a2
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#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
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#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
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#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0_ID 0x7aac
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#define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1_ID 0x7aad
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static const struct pci_device_id intel_eth_pci_id_table[] = {
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static const struct pci_device_id intel_eth_pci_id_table[] = {
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{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
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{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
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@ -739,6 +756,8 @@ static const struct pci_device_id intel_eth_pci_id_table[] = {
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{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0_ID, &adls_sgmii1g_info) },
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{ PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1_ID, &adls_sgmii1g_info) },
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{}
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{}
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};
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};
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MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
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MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
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