mirror of https://gitee.com/openkylin/linux.git
drm/i915: Avoid using PIPE_CONTROL on Ironlake
The workaround is hideous and we are using the STORE_DWORD on all other generations on all other rings, so use for the gen5 render ring as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
160b1543cd
commit
88f23b8fa3
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@ -349,7 +349,7 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
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READ_BREADCRUMB(dev_priv);
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}
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if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
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if (gt_iir & GT_USER_INTERRUPT)
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notify_ring(dev, &dev_priv->ring[RCS]);
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if (gt_iir & bsd_usr_interrupt)
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notify_ring(dev, &dev_priv->ring[VCS]);
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@ -1556,7 +1556,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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GT_BLT_USER_INTERRUPT;
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else
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render_irqs =
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GT_PIPE_NOTIFY |
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GT_USER_INTERRUPT |
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GT_BSD_USER_INTERRUPT;
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I915_WRITE(GTIER, render_irqs);
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POSTING_READ(GTIER);
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@ -207,78 +207,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
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return 0;
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}
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/*
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* 965+ support PIPE_CONTROL commands, which provide finer grained control
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* over cache flushing.
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*/
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struct pipe_control {
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struct drm_i915_gem_object *obj;
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volatile u32 *cpu_page;
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u32 gtt_offset;
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};
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static int
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init_pipe_control(struct intel_ring_buffer *ring)
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{
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struct pipe_control *pc;
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struct drm_i915_gem_object *obj;
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int ret;
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if (ring->private)
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return 0;
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pc = kmalloc(sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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obj = i915_gem_alloc_object(ring->dev, 4096);
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if (obj == NULL) {
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DRM_ERROR("Failed to allocate seqno page\n");
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ret = -ENOMEM;
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goto err;
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}
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obj->agp_type = AGP_USER_CACHED_MEMORY;
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ret = i915_gem_object_pin(obj, 4096, true);
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if (ret)
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goto err_unref;
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pc->gtt_offset = obj->gtt_offset;
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pc->cpu_page = kmap(obj->pages[0]);
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if (pc->cpu_page == NULL)
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goto err_unpin;
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pc->obj = obj;
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ring->private = pc;
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return 0;
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err_unpin:
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i915_gem_object_unpin(obj);
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err_unref:
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drm_gem_object_unreference(&obj->base);
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err:
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kfree(pc);
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return ret;
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}
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static void
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cleanup_pipe_control(struct intel_ring_buffer *ring)
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{
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struct pipe_control *pc = ring->private;
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struct drm_i915_gem_object *obj;
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if (!ring->private)
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return;
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obj = pc->obj;
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kunmap(obj->pages[0]);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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kfree(pc);
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ring->private = NULL;
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}
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static int init_render_ring(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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@ -292,24 +220,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
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I915_WRITE(MI_MODE, mode);
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}
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if (INTEL_INFO(dev)->gen >= 6) {
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} else if (HAS_PIPE_CONTROL(dev)) {
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ret = init_pipe_control(ring);
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if (ret)
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return ret;
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}
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return ret;
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}
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static void render_ring_cleanup(struct intel_ring_buffer *ring)
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{
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if (!ring->private)
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return;
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cleanup_pipe_control(ring);
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}
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static void
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update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
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{
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@ -384,62 +297,6 @@ intel_ring_sync(struct intel_ring_buffer *ring,
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return 0;
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}
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#define PIPE_CONTROL_FLUSH(ring__, addr__) \
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do { \
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intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
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PIPE_CONTROL_DEPTH_STALL | 2); \
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intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
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intel_ring_emit(ring__, 0); \
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intel_ring_emit(ring__, 0); \
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} while (0)
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static int
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pc_render_add_request(struct intel_ring_buffer *ring,
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u32 *result)
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{
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struct drm_device *dev = ring->dev;
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u32 seqno = i915_gem_get_seqno(dev);
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struct pipe_control *pc = ring->private;
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u32 scratch_addr = pc->gtt_offset + 128;
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int ret;
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/*
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* Workaround qword write incoherence by flushing the
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* PIPE_NOTIFY buffers out to memory before requesting
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* an interrupt.
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*/
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ret = intel_ring_begin(ring, 32);
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if (ret)
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return ret;
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intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
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intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128; /* write to separate cachelines */
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
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PIPE_CONTROL_NOTIFY);
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intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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*result = seqno;
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return 0;
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}
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static int
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render_ring_add_request(struct intel_ring_buffer *ring,
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u32 *result)
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@ -468,13 +325,6 @@ ring_get_seqno(struct intel_ring_buffer *ring)
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return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
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}
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static u32
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pc_render_get_seqno(struct intel_ring_buffer *ring)
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{
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struct pipe_control *pc = ring->private;
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return pc->cpu_page[0];
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}
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static void
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render_ring_get_irq(struct intel_ring_buffer *ring)
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{
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@ -488,7 +338,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
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if (HAS_PCH_SPLIT(dev))
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ironlake_enable_graphics_irq(dev_priv,
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GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
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GT_USER_INTERRUPT);
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else
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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@ -509,8 +359,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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if (HAS_PCH_SPLIT(dev))
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ironlake_disable_graphics_irq(dev_priv,
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GT_USER_INTERRUPT |
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GT_PIPE_NOTIFY);
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GT_USER_INTERRUPT);
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else
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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@ -922,7 +771,6 @@ static const struct intel_ring_buffer render_ring = {
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.irq_get = render_ring_get_irq,
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.irq_put = render_ring_put_irq,
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.dispatch_execbuffer = render_ring_dispatch_execbuffer,
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.cleanup = render_ring_cleanup,
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};
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/* ring buffer for bit-stream decoder */
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@ -1157,9 +1005,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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*ring = render_ring;
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if (INTEL_INFO(dev)->gen >= 6) {
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ring->add_request = gen6_add_request;
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} else if (HAS_PIPE_CONTROL(dev)) {
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ring->add_request = pc_render_add_request;
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ring->get_seqno = pc_render_get_seqno;
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}
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if (!I915_NEED_GFX_HWS(dev)) {
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