mirror of https://gitee.com/openkylin/linux.git
ARM: S3C64XX: Define some additional always off clocks
Add entries to clocks_off for some additional clocks which are not currently used by any mainline drivers. They default on at power up but are never actually used so If these blocks are actually supported some of these bindings would need to be redone properly, for example hooking up to the muxes that use them, but that can be done incrementally. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -220,6 +220,107 @@ static struct clk init_clocks_off[] = {
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_DMA1,
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}, {
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.name = "3dse",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_3DSE,
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}, {
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.name = "hclk_secur",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_SECUR,
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}, {
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.name = "sdma1",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_SDMA1,
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}, {
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.name = "sdma0",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_SDMA0,
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}, {
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.name = "hclk_jpeg",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_JPEG,
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}, {
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.name = "camif",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_CAMIF,
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}, {
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.name = "hclk_scaler",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_SCALER,
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}, {
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.name = "2d",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_2D,
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}, {
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.name = "tv",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_TV,
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}, {
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.name = "post0",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_POST0,
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}, {
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.name = "rot",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_ROT,
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}, {
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.name = "hclk_mfc",
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_HCLK_MFC,
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}, {
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.name = "pclk_mfc",
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.parent = &clk_p,
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.enable = s3c64xx_pclk_ctrl,
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.ctrlbit = S3C_CLKCON_PCLK_MFC,
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}, {
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.name = "dac27",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_DAC27,
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}, {
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.name = "tv27",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_TV27,
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}, {
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.name = "scaler27",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_SCALER27,
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}, {
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.name = "sclk_scaler",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_SCALER,
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}, {
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.name = "post0_27",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_POST0_27,
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}, {
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.name = "secur",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_SECUR,
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}, {
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.name = "sclk_mfc",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_MFC,
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}, {
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.name = "cam",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_CAM,
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}, {
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.name = "sclk_jpeg",
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.enable = s3c64xx_sclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_JPEG,
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},
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};
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