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net: hns: select Hilink before serdes loopback for HNS V2 

As Hilink3 and Hilink4 use the same xge training and xge u adaptor for
HNSv2, it needs to select which Hilink to be set before relative serdes
being configed. The hilink_access_sel is the register to do that.

Signed-off-by: Kejian Yan <yankejian@huawei.com>
Signed-off-by: Yisen Zhuang <Yisen.Zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Kejian Yan 2016-06-21 11:56:27 +08:00 committed by David S. Miller
parent 39c9441794
commit 89a6b1aae8
1 changed files with 20 additions and 6 deletions
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26
drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c
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@ -435,11 +435,6 @@ int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
*/
static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
{
/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
*/
u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
const u8 lane_id[] = {
0, /* mac 0 -> lane 0 */
1, /* mac 1 -> lane 1 */
@ -465,11 +460,30 @@ static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
}
if (mac_cb->serdes_ctrl) {
u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
u32 origin;
if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
#define HILINK_ACCESS_SEL_CFG 0x40008
/* hilink4 & hilink3 use the same xge training and
* xge u adaptor. There is a hilink access sel cfg
* register to select which one to be configed
*/
if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
(mac_cb->mac_id <= 3))
dsaf_write_syscon(mac_cb->serdes_ctrl,
HILINK_ACCESS_SEL_CFG, 0);
else
dsaf_write_syscon(mac_cb->serdes_ctrl,
HILINK_ACCESS_SEL_CFG, 3);
}
origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
dsaf_set_field(origin, 1ull << 10, 10, en);
dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
} else {
u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
}