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clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE 

With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.

Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS
as the parent clock is internal to this clock unit.

To avoid duplication of clock definitions, we fix up the parent
reference for A83T in the A83T init function.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Chen-Yu Tsai 2019-05-03 19:31:04 +08:00
parent 4b88915184
commit 89f27fb2dd
1 changed files with 23 additions and 14 deletions
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37
drivers/clk/sunxi-ng/ccu-sun8i-r.c
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@ -73,20 +73,26 @@ static struct ccu_div apb0_clk = {
static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0); static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", /*
0x28, BIT(0), 0); * Define the parent as an array that can be reused to save space
static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", * instead of having compound literals for each gate. Also have it
0x28, BIT(1), 0); * non-const so we can change it on the A83T.
static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", */
0x28, BIT(2), 0); static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw };
static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio",
0x28, BIT(3), 0); apb0_gate_parent, 0x28, BIT(0), 0);
static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir",
0x28, BIT(4), 0); apb0_gate_parent, 0x28, BIT(1), 0);
static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer",
0x28, BIT(6), 0); apb0_gate_parent, 0x28, BIT(2), 0);
static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb",
0x28, BIT(7), 0); apb0_gate_parent, 0x28, BIT(3), 0);
static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart",
apb0_gate_parent, 0x28, BIT(4), 0);
static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c",
apb0_gate_parent, 0x28, BIT(6), 0);
static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd",
apb0_gate_parent, 0x28, BIT(7), 0);
static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
@ -284,6 +290,9 @@ static void __init sunxi_r_ccu_init(struct device_node *node,
static void __init sun8i_a83t_r_ccu_setup(struct device_node *node) static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
{ {
/* Fix apb0 bus gate parents here */
apb0_gate_parent[0] = &a83t_apb0_clk.common.hw;
sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc); sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
} }
CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu", CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",