mirror of https://gitee.com/openkylin/linux.git
MIPS: Move GIC to drivers/irqchip/
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker
Ralf Baechle
parent
8635233ca5
commit
8a19b8f194
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@ -320,7 +320,7 @@ config MIPS_MALTA
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select GENERIC_ISA_DMA
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select HAVE_PCSPKR_PLATFORM
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select IRQ_CPU
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select IRQ_GIC
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select MIPS_GIC
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select HW_HAS_PCI
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select I8253
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select I8259
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@ -362,7 +362,7 @@ config MIPS_SEAD3
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select CPU_MIPSR2_IRQ_EI
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select DMA_NONCOHERENT
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select IRQ_CPU
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select IRQ_GIC
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select MIPS_GIC
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select LIBFDT
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select MIPS_MSC
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select SYS_HAS_CPU_MIPS32_R1
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@ -1073,10 +1073,6 @@ config IRQ_TXX9
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config IRQ_GT641XX
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bool
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config IRQ_GIC
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select MIPS_CM
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bool
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config PCI_GT64XXX_PCI0
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bool
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@ -1890,7 +1886,7 @@ config FORCE_MAX_ZONEORDER
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config CEVT_GIC
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bool "Use GIC global counter for clock events"
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depends on IRQ_GIC && !MIPS_SEAD3
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depends on MIPS_GIC && !MIPS_SEAD3
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help
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Use the GIC global counter for the clock events. The R4K clock
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event driver is always present, so if the platform ends up not
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@ -68,7 +68,6 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
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obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
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obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
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obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
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obj-$(CONFIG_IRQ_GIC) += irq-gic.o
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obj-$(CONFIG_KPROBES) += kprobes.o
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obj-$(CONFIG_32BIT) += scall32-o32.o
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@ -85,7 +85,7 @@ void mips_event_handler(struct clock_event_device *dev)
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*/
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static int c0_compare_int_pending(void)
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{
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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if (cpu_has_veic)
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return gic_get_timer_pending();
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#endif
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@ -119,7 +119,7 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action)
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unsigned long flags;
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int vpflags;
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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if (gic_present) {
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gic_send_ipi_single(cpu, action);
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return;
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@ -158,7 +158,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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static void vsmp_init_secondary(void)
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{
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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/* This is Malta specific: IPI,performance and timer interrupts */
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if (gic_present)
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change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
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@ -70,7 +70,7 @@ static void __init estimate_frequencies(void)
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{
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unsigned long flags;
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unsigned int count, start;
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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unsigned int giccount = 0, gicstart = 0;
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#endif
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@ -87,7 +87,7 @@ static void __init estimate_frequencies(void)
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/* Initialize counters. */
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start = read_c0_count();
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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if (gic_present)
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
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#endif
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@ -97,7 +97,7 @@ static void __init estimate_frequencies(void)
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count();
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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if (gic_present)
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GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
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#endif
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@ -107,7 +107,7 @@ static void __init estimate_frequencies(void)
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count -= start;
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mips_hpt_frequency = count;
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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if (gic_present) {
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giccount -= gicstart;
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gic_frequency = giccount;
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@ -189,7 +189,7 @@ void __init plat_time_init(void)
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setup_pit_timer();
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#endif
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#ifdef CONFIG_IRQ_GIC
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#ifdef CONFIG_MIPS_GIC
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if (gic_present) {
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freq = freqround(gic_frequency, 5000);
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printk("GIC frequency %d.%02d MHz\n", freq/1000000,
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@ -125,3 +125,7 @@ config KEYSTONE_IRQ
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MIPS_GIC
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bool
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select MIPS_CM
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@ -38,3 +38,4 @@ obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
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obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \
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irq-bcm7120-l2.o
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obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
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obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
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